ADC1413D_11 Datasheet, PDF (24/43 Pages) NXP Semiconductors – Dual 14-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps serial JESD204A interface

NXP Semiconductors
ADC1413D series
Dual 14-bit ADC; serial JESD204A interface
Table 13. Output codes versus input voltage …continued
INP  INM (V) Offset binary
Two’s complement
+0.9996338 11 1111 1111 1100
01 1111 1111 1100
+0.9997559 11 1111 1111 1101
01 1111 1111 1101
+0.9998779 11 1111 1111 1110
01 1111 1111 1110
+1
11 1111 1111 1111
01 1111 1111 1111
> +1
11 1111 1111 1111
01 1111 1111 1111
OTR
0
0
0
0
1
11.6 Serial Peripheral Interface (SPI)
11.6.1 Register description
The ADC1413D serial interface is a synchronous serial communications port allowing
easy interfacing with many industry microprocessors. It provides access to the registers
that control the operation of the chip in both read and write modes.
This interface is configured as a 3-wire type (SDIO as bidirectional pin).
SCLK acts as the serial clock, and pin CS acts as the serial chip select.
Each read/write operation is sequenced by the CS signal and enabled by a LOW level to
to drive the chip with 2 bytes to 5 bytes, depending on the content of the instruction byte
(see Table 14).
Table 14. SPI instruction bytes
MSB
Bit
7
6
5
4
3
2
1
Description
R/W^[1] W1
W0
A12 A11
A10
A9
A7
A6
A5
A4
A3
A2
A1
LSB
0
A8
A0
[1] R/W indicates whether a read (logic 1) or write (logic 0) transfer occurs after the instruction byte.
Table 15.
R/W^[1]
0
1
Read or Write mode access description
Description
Write mode operation
Read mode operation
[1] Bits W1 and W0 indicate the number of bytes transferred after the instruction byte.
Table 16.
W1
0
0
1
1
Number of bytes to be transferred
W0
0
1
0
1
Number of bytes transferred
1 byte
2 bytes
3 bytes
4 or more bytes
Bits A12 to A0 indicate the address of the register being accessed. In the case of a
multiple byte transfer, this address is the first register to be accessed. An address counter
is incremented to access subsequent addresses.
ADC1413D_SER
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 9 February 2011
© NXP B.V. 2011. All rights reserved.
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