ADC1413D_11 Datasheet, PDF (22/43 Pages) NXP Semiconductors – Dual 14-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps serial JESD204A interface

NXP Semiconductors
ADC1413D series
Dual 14-bit ADC; serial JESD204A interface
VDDD
50 Ω
CMLPA/CMLPB
10 nF
CMLNA/CMLNB
100 Ω RECEIVER
10 nF
+
−
12 mA to 26 mA
Fig 20. CML output connection to the receiver (AC-coupled)
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11.5 JESD204A serializer
For more information about the JESD204A standard refer to the JEDEC web site.
11.5.1 Digital JESD204A formatter
The block placed after the ADC cores is used to implement all functionalities of the
JESD204A standard. This ensures signal integrity and guarantees the clock and the data
recovery at the receiver side.
The block is highly parameterized and can be configured in various ways depending on
the sampling frequency and the number of lanes used.
M CONVERTERS
L LANES
N bits from Cr₀ +
CS bits for control
TX transport layer
F octets
FRAME
TO
OCTETS
SCRAMBLER
ALIGNMENT
CHARACTER
GENERATOR
8-bit/
10-bit
SER
LANE 0
SYNC~
TX CONTROLLER
N bits from Cr_M−1 +
CS bits for control
samples stream to
lane stream mapping
F octets
FRAME
TO
OCTETS
SCRAMBLER
ALIGNMENT
CHARACTER
GENERATOR
8-bit/
10-bit
N' = N+CS
S samples per frame cycle
CF: position of control bits
HD: frame boundary break
Padding with Tail bits (TT)
Mx(N'xS) bits
Lx(F) octets
L octets
Fig 21. General overview of the JESD204A serializer
SER
LANE 1
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ADC1413D_SER
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 9 February 2011
© NXP B.V. 2011. All rights reserved.
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