PCF8532 Datasheet, PDF (23/44 Pages) NXP Semiconductors – Universal LCD driver for low multiplex rates

NXP Semiconductors
PCF8532
Universal LCD driver for low multiplex rates
PCF8532_1
Product data sheet
Table 8. Definition of PCF8532 commands
Command
Operation code
Bit
7
6
5
4
mode-set
1
1
0
0
load-data-pointer-MSB 0
0
0
0
load-data-pointer-LSB
0
1
0
0
device-select
1
1
1
0
bank-select
1
1
1
1
blink-select
1
1
1
1
frequency-prescaler
1
1
1
0
Reference
3
2
1
0
E B M1 M0 Table 9
P7 P6 P5 P4 Table 10
P3 P2 P1 P0 Table 11
0
0
A1 A0 Table 12
1
0
I
O Table 13
0
A
BF1 BF0 Table 14
1
F2 F1 F0 Table 15
Table 9.
Bit
7 to 4
3
2
1 to 0
Mode-set command bits description
Symbol
Value
Description
-
1100
fixed value
E
display status
0^[1]
disabled (blank)^[2]
1
enabled
B
LCD bias configuration
0^[1]
1
M[1:0]
1_{⁄3 bias}
1_{⁄2 bias}
LCD drive mode selection
01
static; BP0
10
1:2 multiplex; BP0, BP1
11
1:3 multiplex; BP0, BP1, BP2
00^[1]
1:4 multiplex; BP0, BP1, BP2, BP3
[1] Power-on and reset value.
[2] The possibility to disable the display allows implementation of blinking under external control; the enable bit
determines also wether the internal clock signal is available at the CLK pin (see Section 7.5.1).
Table 10.
Bit
7 to 4
3 to 0
Load-data-pointer-MSB command bits description
Symbol
Value
Description
-
0000
fixed value
P[7:4]
0000^[1] to
1001
P7 to P4 defines the first 4 (most significant) bits of
the data pointer that indicates one of the 160 display
RAM addresses
[1] Power-on and reset value.
Table 11.
Bit
7 to 4
3 to 0
Load-data-pointer-LSB command bits description
Symbol
Value
Description
-
0100
fixed value
P[3:0]
0000^[1] to
1111
P3 to P0 defines the last 4 (least significant) bits of the
data pointer that indicates one of the 160 display RAM
addresses
[1] Power-on and reset value.
Rev. 1 — 10 February 2009
© NXP B.V. 2009. All rights reserved.
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