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PCF8532 Datasheet, PDF (1/44 Pages) NXP Semiconductors – Universal LCD driver for low multiplex rates
PCF8532
Universal LCD driver for low multiplex rates
Rev. 1 — 10 February 2009
Product data sheet
1. General description
The PCF8532 is a peripheral device which interfaces to almost any Liquid Crystal Display
(LCD) with low multiplex rates. It generates the drive signals for any static or multiplexed
LCD containing up to four backplanes and up to 160 segments and can easily be
cascaded for larger LCD applications. The PCF8532 is compatible with most
microprocessors or microcontrollers and communicates via a two-line bidirectional
I2C-bus. Communication overheads are minimized by a display RAM with
auto-incremental addressing, by hardware subaddressing and by display memory
switching (static and duplex drive modes).
2. Features
I Single-chip LCD controller and driver for up to 640 elements
I Selectable backplane drive configuration: static or 2, 3 or 4 backplane multiplexing
I 160 segment drives:
N Up to 80 7-segment numeric characters
N Up to 42 14-segment alphanumeric characters
N Any graphics of up to 640 elements
I May be cascaded for large LCD applications (up to 2560 elements possible)
I 160 × 4-bit RAM for display data storage
I Software programmable frame frequency in steps of 5 Hz in the range of 60 Hz to
90 Hz
I Wide LCD supply range: from 2.5 V for low threshold LCDs and up to 8.0 V for
guest-host LCDs and high threshold (automobile) twisted nematic LCDs
I Internal LCD bias generation with voltage-follower buffers
I Selectable display bias configuration: static, 1⁄2 or 1⁄3
I Wide power supply range: from 1.8 V to 5.5 V
I LCD and logic supplies may be separated
I Low power consumption, typically: IDD = 4 µA, IDD(LCD) = 40 µA
I 400 kHz I2C-bus interface
I Auto-incremental display data loading across device subaddress boundaries
I Versatile blinking modes
I Compatible with Chip-On-Glass (COG) technology
I Display memory bank switching in static and duplex drive modes
I No external components
I Manufactured in silicon gate CMOS process
I Two sets of backplane outputs for optimal COG configurations of the application