ADC1113D125 Datasheet, PDF (23/41 Pages) NXP Semiconductors – Dual 11-bit ADC; serial JESD204A interface

NXP Semiconductors
ADC1113D125
ADC1113D125; serial JESD204A interface
Table 13. Output codes
V_INP − V_INM
+0.9970703
Offset binary
111 1111 1100
+0.9980469 111 1111 1101
+0.9990234 111 1111 1110
+1.0000000 111 1111 1111
> +1
111 1111 1111
Two’s complement
011 1111 1100
011 1111 1101
011 1111 1110
011 1111 1111
011 1111 1111
OTR pin
0
0
0
0
1
13.6 Serial Peripheral Interface (SPI)
13.6.1 Register description
The ADC1113D125 serial interface is a synchronous serial communications port allowing
for easy interfacing with many industry microprocessors. It provides access to the
registers that control the operation of the chip in both read and write modes.
This interface is configured as a 3-wire type (SDIO as bidirectional pin).
SCLK acts as the serial clock, and CS acts as the serial chip select bar.
Each read/write operation is sequenced by the CS signal and enabled by a LOW level to
to drive the chip with 2 bytes to 5 bytes, depending on the content of the instruction byte
(see Table 14).
Table 14. Instruction bytes for the SPI
MSB
Bit
7
6
5
4
3
2
1
Description
R/W^[1] W1
W0
A12 A11
A10
A9
A7
A6
A5
A4
A3
A2
A1
[1] R/W indicates whether a read or write transfer occurs after the instruction byte
LSB
0
A8
A0
Table 15.
R/W^[1]
0
1
Read or Write mode access description
Description
Write mode operation
Read mode operation
[1] Bits W1 and W0 indicate the number of bytes transferred after the instruction byte.
Table 16.
W1
0
0
1
1
Number of bytes to be transferred
W0
0
1
0
1
Number of bytes
1 byte transferred
2 bytes transferred
3 bytes transferred
4 or more bytes transferred
Bits A12 to A0 indicate the address of the register being accessed. In the case of a
multiple byte transfer, this address is the first register to be accessed. An address counter
is incremented to access subsequent addresses.
ADC1113D125_2
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 23 April 2010
© NXP B.V. 2010. All rights reserved.
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