MMPF0200F0AEP Datasheet, PDF (22/114 Pages) NXP Semiconductors – 12 channel configurable power management integrated circuit

FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.2
Table 14. Source of start-up sequence
VDDOTP(V) TBB_POR FUSE_POR_XOR
0
0
0
0
0
1
0
1
x
1.5
x
x
Start-up sequence
None
OTP fuses
TBBOTP registers
Factory defined
16 MHz and 32 kHz clocks
There are two clocks: a trimmed 16 MHz, RC oscillator and an untrimmed 32 kHz, RC oscillator. The 16 MHz oscillator is specified within
-8.0/+8.0%. The 32 kHz untrimmed clock is only used in the following conditions:
• VIN < UVDET
• All regulators are in SLEEP mode
• All regulators are in PFM switching mode
A 32 kHz clock, derived from the 16 MHz trimmed clock, is used when accurate timing is needed under the following conditions:
• During start-up, VIN > UVDET
• PWRON_CFG = 1, for power button debounce timing
In addition, when the 16 MHz is active in the ON mode, the debounce times in Table 25 are referenced to the 32 kHz derived from the
16 MHz clock. The exceptions are the LOWVINI and PWRONI interrupts, which are referenced to the 32 kHz untrimmed clock.
Table 15. 16 MHz clock specifications
Consumer T_A = -40 to 85 °C and Extended Industrial T_A = -40 to 105 °C, V_IN = 2.8 to 4.5 V, LICELL = 1.8 to 3.3 V and typical external
component values. Typical values are characterized at V_IN = 3.6 V, LICELL = 3.0 V, and 25 °C, unless otherwise noted.
Symbol
Parameters
Min.
Typ.
Max.
Units
Notes
V_IN16MHz
Operating Voltage From VIN
f_16MHZ
16 MHz Clock Frequency
f_2MHZ
2.0 MHz Clock Frequency
Notes
26. 2.0 MHz clock is derived from the 16 MHz clock.
2.8
–
4.5
V
14.7
16
17.3
MHz
1.84
–
2.16
MHz
(26)
6.2.1 Clock adjustment
The 16 MHz clock and hence the switching frequency of the regulators, can be adjusted to improve the noise integrity of the system. By
changing the factory trim values of the 16MHz clock, the user may add an offset as small as ±3.0% of the nominal frequency.
6.3 Bias and references block description
6.3.1 Internal core voltage references
All regulators use the main bandgap as the reference. The main bandgap is bypassed with a capacitor at VCOREREF. The bandgap and
the rest of the core circuitry are supplied from VCORE. The performance of the regulators is directly dependent on the performance of the
bandgap. No external DC loading is allowed on VCORE, VCOREDIG, or VCOREREF. VCOREDIG is kept powered as long as there is a
valid supply and/or valid coin cell. Table 16 shows the main characteristics of the core circuitry.
PF0200
22
NXP Semiconductors