LPC11E36 Datasheet, PDF (20/66 Pages) NXP Semiconductors – 32-bit ARM Cortex-M0 microcontroller up to 128 kB flash up to 12 kB SRAM and 4 kB EEPROM USART

NXP Semiconductors
LPC11E3x
32-bit ARM Cortex-M0 microcontroller
7.11 SSP serial I/O controller
The SSP controllers operate on a SSP, 4-wire SSI, or Microwire bus. It can interact with
multiple masters and slaves on the bus. Only a single master and a single slave can
communicate on the bus during a given data transfer. The SSP supports full duplex
transfers, with frames of 4 bit to 16 bit of data flowing from the master to the slave and
from the slave to the master. In practice, often only one of these data flows carries
meaningful data.
7.11.1 Features
• Maximum SSP speed of 25 Mbit/s (master) or 4.17 Mbit/s (slave) (in SSP mode)
• Compatible with Motorola SPI (Serial Peripheral Interface), 4-wire Texas Instruments
SSI (Serial Synchronous Interface), and National Semiconductor Microwire buses
• Synchronous serial communication
• Master or slave operation
• 8-frame FIFOs for both transmit and receive
• 4-bit to 16-bit frame
7.12 I²C-bus serial I/O controller
The LPC11E3x contain one I²C-bus controller.
The I²C-bus is bidirectional for inter-IC control using only two wires: a Serial CLock line
(SCL) and a Serial DAta line (SDA). Each device is recognized by a unique address and
can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I²C-bus is a multi-master bus, and
more than one bus master connected to the interface can be controlled the bus.
7.12.1 Features
• The I²C-interface is an I²C-bus compliant interface with open-drain pins. The I²C-bus
interface supports Fast-mode Plus with bit rates up to 1 Mbit/s.
• Easy to configure as master, slave, or master/slave.
• Programmable clocks allow versatile rate control.
• Bidirectional data transfer between masters and slaves.
• Multi-master bus (no central master).
• Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
• Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
• Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
• The I²C-bus can be used for test and diagnostic purposes.
• The I²C-bus controller supports multiple address recognition and a bus monitor mode.
LPC11E3X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 21 November 2013
© NXP B.V. 2013. All rights reserved.
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