PHD77NQ03T Datasheet, PDF (2/13 Pages) NXP Semiconductors – N-channel TrenchMOS FET

NXP Semiconductors
PHD/PHU77NQ03T
N-channel TrenchMOS FET
3. Ordering information
Table 2. Ordering information
Type number
Package
Name
PHD77NQ03T
DPAK
PHU77NQ03T
IPAK
Description
plastic single-ended surface-mounted package; 3 leads
(one lead cropped)
plastic single-ended package; 3 leads (in-line)
4. Limiting values
Table 3. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
V_DS
drain-source voltage
25 °C ≤ T_j ≤ 175 °C
-
V_DGR drain-gate voltage (DC)
25 °C ≤ T_j ≤ 175 °C; R_GS = 20 kΩ
-
V_GS
gate-source voltage
-
I_D
drain current
T_mb = 25 °C; V_GS = 10 V; see Figure 2 and 3
-
T_mb = 100 °C; V_GS = 10 V; see Figure 2
-
I_DM
peak drain current
T_mb = 25 °C; pulsed; t_p ≤ 10 µs; see Figure 3
-
P_tot
total power dissipation
T_mb = 25 °C; see Figure 1
-
T_stg
storage temperature
−55
T_j
junction temperature
−55
Source-drain diode
I_S
source current
T_mb = 25 °C
-
I_SM
peak source current
T_mb = 25 °C; pulsed; t_p ≤ 10 µs
-
Avalanche ruggedness
E_DS(AL)S non-repetitive drain-source
unclamped inductive load; I_D = 32 A;
-
avalanche energy
t_p = 0.17 ms; V_DS ≤ 25 V; R_GS = 50 Ω;
V_GS = 10 V; starting at T_j = 25 °C
Version
SOT428
SOT533
Max Unit
25
V
25
V
±20
V
75
A
55.9 A
240
A
107
W
+175 °C
+175 °C
75
A
240
A
100
mJ
PHD_PHU77NQ03T_1
Product data sheet
Rev. 01 — 28 November 2006
© NXP B.V. 2006. All rights reserved.
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