PHD108NQ03LT Datasheet, PDF (2/12 Pages) NXP Semiconductors – N-channel TrenchMOS logic level FET

NXP Semiconductors
PHD108NQ03LT
N-channel TrenchMOS logic level FET
2. Pinning information
Table 2. Pinning information
Pin
Symbol Description
1
G
gate
2
D
drain
3
S
source
mb
D
mounting base; connected to
drain
[1] It is not possible to make a connection to pin 2.
Simplified outline
mb
[1]
2
1
3
SOT428
(SC-63; DPAK)
3. Ordering information
Graphic symbol
D
G
mbb076 S
Table 3. Ordering information
Type number
Package
Name
Description
PHD108NQ03LT SC-63;
DPAK
plastic single-ended surface-mounted package (DPAK); 3 leads (one
lead cropped)
4. Limiting values
Version
SOT428
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
V_DS
V_DGR
V_GS
I_D
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
I_DM
peak drain current
P_tot
total power dissipation
T_stg
storage temperature
T_j
junction temperature
Source-drain diode
T_j ≥ 25 °C; T_j ≤ 175 °C
T_j ≥ 25 °C; T_j ≤ 175 °C; R_GS = 20 kΩ
V_GS = 5 V; T_mb = 25 °C; see Figure 1; see Figure 3
V_GS = 5 V; T_mb = 100 °C; see Figure 1
t_p ≤ 10 µs; pulsed; T_mb = 25 °C; see Figure 3
T_mb = 25 °C; see Figure 2
I_S
source current
I_SM
peak source current
Avalance ruggedness
T_mb = 25 °C
t_p ≤ 10 µs; pulsed; T_mb = 25 °C
E_DS(AL)S
non-repetitive
V_GS = 10 V; T_j(init) = 25 °C; I_D = 43 A; V_sup ≤ 25 V;
drain-source avalanche unclamped; t_p = 0.25 ms; R_GS = 50 Ω
energy
Min Max Unit
-
25
V
-
25
V
-20 20
V
-
75
A
-
75
A
-
240 A
-
187 W
-55 175 °C
-55 175 °C
-
75
A
-
240 A
-
180 mJ
PHD108NQ03LT_4
Product data sheet
Rev. 04 — 5 June 2009
© NXP B.V. 2009. All rights reserved.
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