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PHD108NQ03LT Datasheet, PDF (1/12 Pages) NXP Semiconductors – N-channel TrenchMOS logic level FET | |||
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PHD108NQ03LT
N-channel TrenchMOS logic level FET
Rev. 04 â 5 June 2009
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industrial applications only.
1.2 Features and benefits
 Low conduction losses due to low
on-state resistance
 Simple gate drive required due to low
gate charge
 Suitable for logic level gate drive
sources
1.3 Applications
 DC-to-DC convertors
 Switched-mode power supplies
1.4 Quick reference data
Table 1. Quick reference
Symbol Parameter
Conditions
VDS
drain-source voltage Tj ⥠25 °C; Tj ⤠175 °C
ID
drain current
Tmb = 25 °C; VGS = 5 V; see
Figure 1; see Figure 3
Ptot
total power
dissipation
Tmb = 25 °C; see Figure 2
Avalance ruggedness
EDS(AL)S non-repetitive
drain-source
avalanche energy
Dynamic characteristics
VGS = 10 V; Tj(init) = 25 °C;
ID = 43 A; Vsup ⤠25 V;
unclamped; tp = 0.25 ms;
RGS = 50 â¦
QGD
gate-drain charge VGS = 4.5 V; ID = 25 A;
VDS = 12 V; Tj = 25 °C; see
Figure 12; see Figure 13
Static characteristics
RDSon
drain-source
on-state resistance
VGS = 10 V; ID = 25 A;
Tj = 25 °C; see Figure 10;
see Figure 11
Min Typ Max Unit
-
-
25 V
-
-
75 A
-
-
187 W
-
-
180 mJ
-
5.6 -
nC
-
5.3 6
mâ¦
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