74HC02D652 Datasheet, PDF (2/16 Pages) NXP Semiconductors – Quad 2-input NOR gate

NXP Semiconductors
4. Functional diagram
74HC02; 74HCT02
Quad 2-input NOR gate
2 1A
3 1B
5 2A
6 2B
8 3A
9 3B
11 4A
12 4B
1Y 1
2Y 4
3Y 10
4Y 13
mna216
Fig 1. Logic symbol
2
≥1
3
1
5
≥1
6
4
8
≥1
9
10
11
≥1
12
13
001aah084
Fig 2. IEC logic symbol
5. Pinning information
5.1 Pinning
A
Y
B
mna215
Fig 3. Logic diagram (one gate)
1Y 1
1A 2
1B 3
2Y 4
2A 5
2B 6
GND 7
14 V_CC
13 4Y
12 4B
02
11 4A
10 3Y
9 3B
8 3A
001aac919
terminal 1
index area
1A 2
1B 3
2Y 4
2A 5
2B 6
02
GND⁽¹⁾
13 4Y
12 4B
11 4A
10 3Y
9 3B
001aac920
Transparent top view
Fig 4. Pin configuration DIP14, SO14 and (T)SSOP14
(1) The die substrate is attached to this pad using
conductive die attach material. It cannot be used as a
supply pin or input.
Fig 5. Pin configuration DHVQFN14
5.2 Pin description
Table 2.
Symbol
1Y to 4Y
1A to 4A
1B to 4B
GND
V_CC
Pin description
Pin
1, 4, 10, 13
2, 5, 8, 11
3, 6, 9,12
7
14
Description
data output
data input
data input
ground (0 V)
supply voltage
74HC_HCT02
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 4 September 2012
© NXP B.V. 2012. All rights reserved.
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