74AHC00 Datasheet, PDF (2/13 Pages) NXP Semiconductors – Quad 2-input NAND gate

NXP Semiconductors
4. Functional diagram
74AHC00; 74AHCT00
Quad 2-input NAND gate
1 1A
2 1B
4 2A
5 2B
9 3A
10 3B
12 4A
13 4B
1Y 3
2Y 6
3Y 8
4Y 11
mna212
Fig 1. Logic symbol
1
&
3
2
4
&
6
5
9
&
8
10
12
&
11
13
mna246
Fig 2. IEC logic symbol
5. Pinning information
5.1 Pinning
A
Y
B
mna211
Fig 3. Logic diagram (one gate)
1A 1
1B 2
1Y 3
2A 4
2B 5
2Y 6
GND 7
14 V_CC
13 4B
12 4A
00
11 4Y
10 3B
9 3A
8 3Y
001aac938
Fig 4. Pin configuration SO14 and TSSOP14
terminal 1
index area
1B 2
1Y 3
2A 4
2B 5
2Y 6
00
GND ⁽¹⁾
13 4B
12 4A
11 4Y
10 3B
9 3A
001aac939
Transparent top view
(1) The die substrate is attached to this pad using
conductive die attach material. It can not be used as
a supply pin or input.
Fig 5. Pin configuration DHVQFN14
5.2 Pin description
Table 2.
Symbol
1A
1B
1Y
2A
2B
2Y
GND
Pin description
Pin
1
2
3
4
5
6
7
Description
data input
data input
data output
data input
data input
data output
ground (0 V)
74AHC_AHCT00_3
Product data sheet
Rev. 03 — 8 January 2008
© NXP B.V. 2008. All rights reserved.
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