ADC1213D Datasheet, PDF (19/41 Pages) NXP Semiconductors – Dual 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps

NXP Semiconductors
ADC1213D series
ADC1213D series
Sine
clock input
CLKP
CLKM
Sine
clock input
CLKP
CLKM
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a. Sine clock input
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b. Sine clock input (with transformer)
LVDS
clock input
CLKP
CLKM
LVPECL
clock input
CLKP
CLKM
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c. LVDS clock input
Fig 17. Differential clock input
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d. LVPECL clock input
14.3.2 Equivalent input circuit
The equivalent circuit of the input clock buffer is shown in Figure 18. The common-mode
voltage of the differential input stage is set via internal resistors of 5 kΩ resistors.
Package
ESD
Parasitics
CLKP
CLKM
V_cm(clk)
SE_SEL SE_SEL
5 kΩ
5 kΩ
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Fig 18. Equivalent input circuit
Single-ended or differential clock inputs can be selected via the SPI (see Table 20). If
single-ended is selected, the input pin (CLKM or CLKP) is selected via control bit
SE_SEL.
ADC1213D_SER_5
Preliminary data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 05 — 23 April 2010
© NXP B.V. 2010. All rights reserved.
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