MKL82Z128VMC7 Datasheet, PDF (18/133 Pages) NXP Semiconductors – 72 MHz ARM® Cortex®-M0+ with 128 KB Flash and 96 KB SRAM

Overview
Table 7. Wakeup sources for LLWU inputs (continued)
LLWU pins
LLWU_M1IF
LLWU_M2IF
LLWU_M3IF
LLWU_M4IF
LLWU_M5IF
LLWU_M6IF
LLWU_M7IF
Module sources or pin names
CMP0
Reserved
Reserved
TSI0²
RTC alarm
Reserved
RTC second
1. A wakeup source of LLWU, USB0_DP or USB0_DM is available only when the chip is in USB host mode.
2. Requires the peripheral and the peripheral interrupt to be enabled. The LLWU_ME[WUMEn] (n=0-7) bit enables the
internal module flag a wakeup inputs. After wakeup, the flags are cleared based on the peripheral clearing mechanism.
2.1.10 Debug controller
This device supports standard ARM 2-pin SWD debug port. It provides register and
memory accessibility from the external debugger interface, basic run/halt control plus 2
breakpoints and 2 watchpoints.
It also supports trace function with the Micro Trace Buffer (MTB), which provides a
simple execution trace capability for the Cortex-M0+ processor.
2.1.11 INTMUX
The Interrupt Multiplexer (INTMUX) routes the interrupt sources to the interrupt
outputs. It provides interrupt status registers to monitor interrupt pending status and
vector numbers and implements the ability to logical AND or OR enabled interrupts on
a given channel.
The INTMUX has the following features:
• Supports 4 multiplex channels
• Each channel receives 32 interrupt sources and has one interrupt output
• Each interrupt source can be enabled or disabled
• Each channel supports logic AND or logic OR of all enabled interrupt sources
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NXP Semiconductors
Kinetis KL82 Microcontroller, Rev. 3, 08/2016