LPC2880 Datasheet, PDF (18/43 Pages) NXP Semiconductors – 16/32-bit ARM microcontrollers; 8 kB cache, up to 1 MB flash, Hi-Speed USB 2.0 device, and SDRAM memory interface

NXP Semiconductors
LPC2880; LPC2888
16/32-bit ARM microcontrollers with external memory interface
6.9 Event router
88 external and 11 internal LPC2880/2888 signals are connected to the Event Router
block. GPIO input pins, functional input pins, and even functional outputs can be
monitored by the Event Router.
Each signal can act as an interrupt source or a clock-enable for LPC2880/2888 modules,
with individual options for high- or low-level sensitivity or rising- or falling-edge sensitivity.
The outputs of the polarity and sensitivity logic can be read from Raw Status Registers 0
to 3.
Each active state is next masked/enabled by a “global” mask bit for that signal. The results
can be read from Pending Registers 0 to 3.
All 99 Pending signals are presented to each of the five output logic blocks. Each output
logic block includes a set of four Interrupt Output Mask Registers, each set totalling
99 bits, that control whether each signal applies to that output. These are logically ANDed
with the corresponding Pending signals, and the 99 results in each logic block are logically
ORed to make the output of the block. The 496 results can be read in the Interrupt Output
Pending Registers.
Outputs 0 to 3 are routed to the Interrupt Controller, in which each can be individually
enabled to cause an interrupt. Output 4 is routed to the Clock Generation Unit, in which it
can serve to enable clocking for selected clock domains. The five outputs can be read in
the Output Register.
6.10 General purpose timers
The LPC2880/2888 contains two fully independent general purpose timers. Each timer is
a 32 bit wide down counter with a selectable prescaler. The prescaler allows either the
system clock to be used directly, or the clock to be divided by 16 or 256.
Two modes of operation are available, free-running and periodic timer. In periodic timer
mode, the counter will generate an interrupt at a constant interval. In free-running mode
the timer will overflow after reaching its zero value and continue to count down from the
maximum value.
6.10.1 Features
• Two independent 32-bit timers.
• Free-running or periodic operating modes.
• Generate timed interrupts.
6.11 Watchdog timer
The purpose of the watchdog timer is to interrupt and/or reset the microcontroller within a
reasonable amount of time if it enters an erroneous state. When enabled, the watchdog
will generate an interrupt or a system reset if the user program fails to reset the watchdog
within a predetermined amount of time. Alternatively, it can be used as an additional
general purpose Timer.
LPC2880_LPC2888_3
Preliminary data sheet
Rev. 03 — 17 April 2008
© NXP B.V. 2008. All rights reserved.
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