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LPC2880 Datasheet, PDF (1/43 Pages) NXP Semiconductors – 16/32-bit ARM microcontrollers; 8 kB cache, up to 1 MB flash, Hi-Speed USB 2.0 device, and SDRAM memory interface
LPC2880; LPC2888
16/32-bit ARM microcontrollers; 8 kB cache, up to 1 MB flash,
Hi-Speed USB 2.0 device, and SDRAM memory interface
Rev. 03 — 17 April 2008
Preliminary data sheet
1. General description
The LPC2880/2888 is an ARM7-based microcontroller for portable applications requiring
low power and high performance. It includes a USB 2.0 Hi-Speed device interface, an
external memory interface that can interface to SDRAM and flash, an SD/MMC memory
card interface, ADC and DACs, and serial interfaces including UART, I2C-bus, and
I2S-bus. Architectural enhancements like multi-channel DMA, processor cache,
simultaneous operations on multiple internal buses, and flexible clock generation help
ensure that the LPC2880/2888 can handle more demanding applications than many
competing devices. The chip can be powered from a single battery, from the USB, or from
regulated 1.8 V and 3.3 V.
2. Features
2.1 Key features
I ARM7TDMI processor with 8 kB cache, operating at up to 60 MHz
I 1 MB on-chip flash program memory with 128-bit access for high performance
I 64 kB SRAM
I Boot ROM allows execution of flash code, external code, or flash programming via
USB
I On-chip DC-to-DC converter can generate all required voltages from a single battery
or from USB power
I Multiple internal buses allow simultaneous simple DMA, USB DMA, and program
execution from on-chip flash without contention
I External memory controller supports flash, SRAM, ROM, and SDRAM
I Advanced vectored interrupt controller, supporting up to 30 vectored interrupts
I Innovative event router allows interrupt, power-up, and clock-start capabilities from up
to 107 sources
I Multi-channel general purpose DMA controller that can be used with most on-chip
peripherals as well as for memory-to-memory transfers
I Serial interfaces:
N Hi-Speed or Full-Speed USB 2.0 device (480 Mbit/s or 12 Mbit/s) with on-chip
physical layer
N UART with fractional baud rate generation, flow control, IrDA support, and FIFOs
N I2C-bus interface
N I2S-bus (Inter IC Sound bus) interface for independent stereo digital audio input
and output
I SD/MMC memory card interface