LPC1102_11 Datasheet, PDF(14/39 Page) NXP Semiconductors – 32-bit ARM Cortex-M0 microcontroller; 32 kB flash and 8 kB SRAM

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LPC1102_11 Datasheet, PDF (14/39 Pages) NXP Semiconductors – 32-bit ARM Cortex-M0 microcontroller; 32 kB flash and 8 kB SRAM

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NXP Semiconductors

LPC1102

32-bit ARM Cortex-M0 microcontroller

Six of the GPIO pins (see Table 3) serve as external wake-up pins to a dedicated start

logic to wake up the chip from Deep-sleep mode.

The clock source should be switched to IRC before entering Deep-sleep mode unless the

watchdog oscillator remains running in Deep-sleep mode. The IRC can be switched on

and off glitch-free and provides a clean clock signal after start-up.

7.15 System control

7.15.1 Start logic

The start logic connects external pins to corresponding interrupts in the NVIC. Each pin

shown in Table 3 as input to the start logic has an individual interrupt in the NVIC interrupt

vector table. The start logic pins can serve as external interrupt pins when the chip is

running. In addition, an input signal on the start logic pins can wake up the chip from

Deep-sleep mode when all clocks are shut down.

The start logic must be configured in the system configuration block and in the NVIC

before being used.

7.15.2 Reset

Reset has four sources on the LPC1102: the RESET pin, the Watchdog reset, power-on

reset (POR), and the BrownOut Detection (BOD) circuit. In addition, there is an ARM

software reset. The RESET pin is a Schmitt trigger input pin. Assertion of chip reset by

any source, once the operating voltage attains a usable level, starts the IRC and initializes

the flash controller.

A LOW-going pulse as short as 50 ns resets the part.

When the internal Reset is removed, the processor begins executing at address 0, which

is initially the Reset vector mapped from the boot block. At that point, all of the processor

and peripheral registers have been initialized to predetermined values.

7.15.3 Brownout detection

The LPC1102 includes four levels for monitoring the voltage on the VDD pin. If this voltage

falls below one of the four selected levels, the BOD asserts an interrupt signal to the

NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC

in order to cause a CPU interrupt; if not, software can monitor the signal by reading a

dedicated status register. Four additional threshold levels can be selected to cause a

forced reset of the chip.

7.15.4 Code security (Code Read Protection - CRP)

This feature of the LPC1102 allows user to enable different levels of security in the system

so that access to the on-chip flash and use of the Serial Wire Debugger (SWD) can be

restricted. When needed, CRP is invoked by programming a specific pattern into a

dedicated flash location. IAP commands are not affected by the CRP.

There are three levels of Code Read Protection:

1. CRP1 disables access to the chip via the SWD and allows partial flash update

(excluding flash sector 0). This mode is useful when CRP is required and flash field

updates are needed but all sectors can not be erased.

LPC1102

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 3 â 18 April 2011

14 of 39

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