LPC1102_11 Datasheet, PDF (10/39 Pages) NXP Semiconductors – 32-bit ARM Cortex-M0 microcontroller; 32 kB flash and 8 kB SRAM

NXP Semiconductors
LPC1102
32-bit ARM Cortex-M0 microcontroller
• Measurement range 0 V to V_DD.
• 10-bit conversion time ≥ 2.44 μs.
• Burst conversion mode for single or multiple inputs.
• Optional conversion on transition of input pin or timer match signal.
• Individual result registers for each ADC channel to reduce interrupt overhead.
7.11 General purpose external event counter/timers
The LPC1102 includes two 32-bit counter/timers and two 16-bit counter/timers. The
counter/timer is designed to count cycles of the system derived clock. It can optionally
generate interrupts or perform other actions at specified timer values, based on four
match registers. Each counter/timer also includes one capture input to trap the timer value
when an input signal transitions, optionally generating an interrupt.
7.11.1 Features
• A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler.
• Counter or timer operation.
• One capture channel that can take a snapshot of the timer value when an input signal
transitions. A capture event may also generate an interrupt.
• Four match registers per timer that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
• Up to four external outputs corresponding to match registers, with the following
capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
7.12 System tick timer
The ARM Cortex-M0 includes a system tick timer (SYSTICK) that is intended to generate
a dedicated SYSTICK exception at a fixed time interval (typically 10 ms).
7.13 Watchdog timer
The purpose of the watchdog is to reset the microcontroller within a selectable time
period.
7.13.1 Features
• Internally resets chip if not periodically reloaded.
• Debug mode.
• Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be
disabled.
LPC1102
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 18 April 2011
© NXP B.V. 2011. All rights reserved.
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