DAC1405D650 Datasheet, PDF (14/43 Pages) NXP Semiconductors – Dual 14-bit DAC, up to 650 Msps; 2´ 4´ and 8´ interpolating

NXP Semiconductors
DAC1405D650
Dual 14-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating
RESET_N
(optional)
SCS_N
SCLK
SDIO
R/W N1 N0 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
SDO
(optional)
D7 D6 D5 D4 D3 D2 D1 D0
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R/W indicates the mode access, (see Table 6):
Fig 3. SPI protocol
Table 6.
R/W
0
1
Read or Write mode access description
Description
Write mode operation
Read mode operation
In Table 7 below N1 and N0 indicate the number of bytes transferred after the instruction
byte.
Table 7.
N1
0
0
1
1
Number of bytes to be transferred
N0
Number of bytes
0
1 byte transferred
1
2 bytes transferred
0
3 bytes transferred
1
4 bytes transferred
A[4:0]: indicates which register is being addressed. In the case of a multiple transfer, this
address concerns the first register after which the next registers follow directly in a
decreasing order according to Table 9 “Register allocation map”.
10.2.2 SPI timing description
The SPI interface can operate at a frequency of up to 15 MHz. The SPI timing is shown in
Figure 4.
DAC1405D650_1
Product data sheet
Rev. 01 — 4 May 2009
© NXP B.V. 2009. All rights reserved.
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