DAC1405D650 Datasheet, PDF (1/43 Pages) NXP Semiconductors – Dual 14-bit DAC, up to 650 Msps; 2´ 4´ and 8´ interpolating

DAC1405D650
Dual 14-bit DAC, up to 650 Msps; 2× 4× and 8× interpolating
Rev. 01 — 4 May 2009
Product data sheet
1. General description
The DAC1405D650 is a high-speed 14-bit dual channel Digital-to-Analog Converter (DAC)
with selectable 2×, 4× or 8× interpolating filters optimized for multi-carrier wireless
transmitters.
Thanks to its digital on-chip modulation, the DAC1405D650 allows the complex I and Q
inputs to be converted up from baseband to IF. The mixing frequency is adjusted via a
Serial Peripheral Interface (SPI) with a 32-bit Numerically Controlled Oscillator (NCO) and
the phase is controlled by a 16-bit register.
Two modes of operation are available: separate data ports or a single interleaved
high-speed data port. In the Interleaved mode, the input data stream is demultiplexed into
its original I and Q data and then latched.
The DAC1405D650 also includes a 2×, 4× and 8× clock multiplier which provides the
appropriate internal clocks and an internal regulator to adjust the output full-scale current.
2. Features
I Dual 14-bit resolution
I 650 Msps maximum update rate
I IMD3: 80 dBc; f_s = 640 Msps; f_o = 96 MHz
I ACPR: 71 dBc; 2 carriers WCDMA;
f_s = 614.4 Msps; f_o = 96 MHz; PLL on
I Selectable 2×, 4× or 8× interpolation I Typical 0.95 W power dissipation at 4×
filters
interpolation
I Input data rate up to 160 Msps
I Power-down and Sleep modes
I Very low noise cap-free integrated PLL I Differential scalable output current from
1.6 mA to 22 mA
I 32-bit programmable NCO frequency I On-chip 1.25 V reference
I Dual port or Interleaved data modes I External analog offset control
(10-bit auxiliary DACs)
I 1.8 V and 3.3 V power supplies
I Internal digital offset control
I LVDS compatible clock
I Inverse (sin x) / x function
I Two’s complement or binary offset I Fully compatible SPI port
data format
I 3.3 V CMOS input buffers
I Industrial temperature range from
−40 °C to +85 °C