SC16IS752 Datasheet, PDF(13/59 Page) NXP Semiconductors – Dual UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support

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SC16IS752 Datasheet, PDF (13/59 Pages) NXP Semiconductors – Dual UART with I2C-bus/SPI interface, 64 bytes of transmit and receive FIFOs, IrDA SIR built-in support

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NXP Semiconductors

SC16IS752/SC16IS762

Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR

7.4 Hardware Reset, Power-On Reset (POR) and Software Reset

These three reset methods are identical and will reset the internal registers as indicated in

Table 4.

Table 4 summarizes the state of register after reset.

Table 4. Register reset

Interrupt Enable Register

Interrupt Identiï¬cation Register

FIFO Control Register

Line Control Register

Modem Control Register

Line Status Register

Modem Status Register

Enhanced Features Register

Receive Holding Register

Transmit Holding Register

Transmission Control Register

Trigger Level Register

Transmit FIFO level

Receive FIFO level

I/O direction

I/O interrupt enable

I/O control

Extra Features Control Register

Reset state

all bits cleared

bit 0 is set; all other bits cleared

all bits cleared

reset to 0001 1101 (0x1D)

all bits cleared

bit 5 and bit 6 set; all other bits cleared

bits 3:0 cleared; bits 7:4 input signals

all bits cleared

pointer logic cleared

all bits cleared

reset to 0100 0000 (0x40)

all bits cleared

Remark: Registers DLL, DLH, SPR, XON1, XON2, XOFF1, XOFF2 are not reset by the

top-level reset signal RESET, POR and Software Reset, that is, they hold their

initialization values during reset.

Table 5 summarizes the state of output signals after reset.

Table 5.

Signal

RTS

I/Os

IRQ

Output signals after reset

Reset state

HIGH

inputs

HIGH by external pull-up

SC16IS752_SC16IS762_7

Product data sheet

Rev. 07 â 19 May 2008

13 of 59

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