74AUP2G86GN Datasheet, PDF (13/21 Pages) NXP Semiconductors – Low-power dual 2-input EXCLUSIVE-OR gate

NXP Semiconductors
74AUP2G86
Low-power dual 2-input EXCLUSIVE-OR gate
XSON8: extremely thin small outline package; no leads;
8 terminals; body 1.35 x 1 x 0.5 mm
E
terminal 1
index area
D
A
A₁
detail X
SOT1089
(4×)⁽²⁾
b4
e
L
5
e₁
(8×)⁽²⁾
1
8
Dimensions
terminal 1
index area
L₁
0
0.5
scale
Unit
A⁽¹⁾ A₁ b
D
E
e
e₁ L
L₁
max 0.5 0.04 0.20 1.40 1.05
0.35 0.40
mm nom
0.15 1.35 1.00 0.55 0.35 0.30 0.35
min
0.12 1.30 0.95
0.27 0.32
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
Outline
version
References
IEC
JEDEC
JEITA
SOT1089
MO-252
1 mm
Fig 12. Package outline SOT1089 (XSON8)
74AUP2G86
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 14 June 2012
X
European
projection
sot1089_po
Issue date
10-04-09
10-04-12
© NXP B.V. 2012. All rights reserved.
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