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| 74AUP2G86GN Datasheet, PDF (10/21 Pages) NXP Semiconductors – Low-power dual 2-input EXCLUSIVE-OR gate | |||
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NXP Semiconductors
74AUP2G86
Low-power dual 2-input EXCLUSIVE-OR gate
VCC
VEXT
G
VI
VO
DUT
5 kΩ
RT
CL
RL
001aac521
Fig 9.
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Test circuit for measuring switching times
Table 10. Test data
Supply voltage
VCC
0.8 V to 3.6 V
Load
CL
5 pF, 10 pF, 15 pF and 30 pF
RL[1]
5 kï or 1 Mï
VEXT
tPLH, tPHL
open
[1] For measuring enable and disable times RL = 5 kï.
For measuring propagation delays, set-up and hold times and pulse width RL = 1 Mï.
tPZH, tPHZ
GND
tPZL, tPLZ
2 ï´ VCC
74AUP2G86
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 â 14 June 2012
© NXP B.V. 2012. All rights reserved.
10 of 21
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