PCA9541_08 Datasheet, PDF (11/43 Pages) NXP Semiconductors – 2-to-1 I2C-bus master selector with interrupt logic and reset

NXP Semiconductors
PCA9541
2-to-1 I²C-bus master selector with interrupt logic and reset
Table 6. Register 0 - Interrupt Enable (IE) register bit description …continued
Legend: * default value
Bit Symbol
Access Value^[1] Description
1
BUSINITMSK R/W 0*
After connection is requested and Bus Initialization requested (BUSINIT = 1),
an interrupt on INT will be generated when the bus initialization is done.
Remark: Channel switching is done after bus initialization completed.
1
After connection is requested and Bus Initialization requested (BUSINIT = 1),
an interrupt on INT will not be generated when the bus initialization is done
(masked).
Remark: Channel switching is done after bus initialization completed.
0
INTINMSK
R/W 0*
Interrupt on INT_IN will generate an interrupt on INT.
1
Interrupt on INT_IN will not generate an interrupt on INT (masked)
[1] Default values are the same for PCA9541/01, PCA9541/02, PCA9541/03.
8.3.2 Register 1: Control Register (B1:B0 = 01b)
The Control Register described below is identical for both the masters. Nevertheless,
there are physically 2 internal Control Registers, one for each upstream channel. When
master 0 reads/writes in this register, the internal Control Register 0 will be accessed.
When master 1 reads/writes in this register, the internal Control Register 1 will be
accessed.
Table 7. Register 1 - Control Register (B1:B0 = 01b) bit allocation
7
6
5
4
3
NTESTON TESTON
0
BUSINIT
NBUSON
2
BUSON
1
NMYBUS
0
MYBUS
Table 8. Register 1 - Control Register (B1:B0 = 01b) bit description
Legend: * default value
Bit Symbol
Access Value^[1]
Description
7
NTESTON R/W 0*
A logic level HIGH to the INT line of the other channel is sent (interrupt
cleared).
1
A logic level LOW to the INT line of the other channel is sent (interrupt
generated).
6
TESTON
R/W 0*
A logic level HIGH to the INT line is sent (interrupt cleared).
1
A logic level LOW to the INT line is sent (interrupt generated).
5
-
R only 0*
not used
4
BUSINIT
R/W 0*
Bus initialization is not requested.
1
Bus initialization is requested.
3
NBUSON R only see
NBUSON bit along with BUSON bit decides whether any upstream channel
Table 11 is connected to the downstream channel or not. See Table 10, Table 11, and
Table 12.
2
BUSON
R/W see
BUSON bit along with the NBUSON bit decides whether any upstream
Table 11 channel is connected to the downstream channel or not. See Table 10,
Table 11, and Table 12.
1
NMYBUS R only see
NMYBUS bit along with MYBUS bit decides which upstream channel is
Table 11 connected to the downstream channel. See Table 9, Table 11, and Table 12.
0
MYBUS
R/W see
MYBUS bit along with the NMYBUS bit decides which upstream channel is
Table 11 connected to the downstream channel. See Table 9, Table 11, and Table 12.
[1] Default values are the same for PCA9541/01, PCA9541/02, PCA9541/03.
PCA9541_6
Product data sheet
Rev. 06 — 11 September 2008
© NXP B.V. 2008. All rights reserved.
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