AN11275 Datasheet, PDF (11/20 Pages) NXP Semiconductors – SGPIO on the LPC4300

NXP Semiconductors
AN11275
SGPIO on the LPC4300
4.2.6 CTRL_ENABLE
With the CTRL_ENABLE register set to 1 for a particular bit the corresponding slice’s 12-
bit COUNT down counter or external shift clock is started to provide the data shift clock
for the slice.
4.2.7 CTRL_DISABLE
With the CTRL_DISABLE register set to 1 for a particular bit the corresponding slice’s
COUNT clocks or external shift clock is disabled. When this register is set, it
synchronously disables the POSx counter when POSx counter reaches a zero count.
The CTRL_DISABLED register is not cleared at that time: it remains set.
Tip 5. When starting COUNTx (by setting CTRL_ENABLE), this register should be set
after COUNTx is started with register CTRL_ENABLE.
4.3 SGPIO interrupt specific registers
For these interrupt specific registers, replace the x with the correct number for the
interrupt. 0 for shift clock; 1 for main register and shadow register exchange; 2 for data
pattern match and 3 for input bit match.
4.3.1 CLR_EN_x
This register is used to disable interrupts. Slice interrupts can be disabled by writing a 1
to the register. For example, if a 1 is written to bit 2 the interrupt for slice C will be
disabled.
4.3.2 SET_EN_x
This register is used to enable interrupts. Slice interrupts can be enabled by writing a 1 to
the register. If, for example, a 1 is written to bit 3 the interrupt for slice D will be enabled.
4.3.3 ENABLE_x
Reading out this register will return what slices have their interrupts enabled. If this
register contains the value 0b1001 that means slice A and D have the interrupts enabled.
4.3.4 STATUS_x
Reading out this register will return on which slices an interrupt has happened. It is
possible that an interrupt happens on multiple slices at the same time. If this register
contains the value 0b1000100 interrupts happened on slice C and G.
4.3.5 CTR_STAT_x
This register is used to clear the interrupt state. It is recommended to clear all interrupt
states after handling the interrupts otherwise the value in the STATUS_x register will also
contain old interrupt states.
4.3.6 SET_STAT_x
This register is used to set interrupt states. When a 1 is written to bit 0 it will look like an
interrupt happened on slice A. This register can be used for code testing.
4.4 SGPIO pin control registers
These registers are used to control SGPIO pin status. GPIO_INREG, GPIO_OUTREG
and GPIO_OENREG are SGPIO pin based. This means that they control SGPIO pins
and not slices. If a 1 is written to bit 2 this will effect SGPIO pin 2 and not slice C.
AN11275
Application note
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
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