AN11275 Datasheet, PDF (10/20 Pages) NXP Semiconductors – SGPIO on the LPC4300

NXP Semiconductors
AN11275
SGPIO on the LPC4300
0b01 for falling edge, 0b10 for low level, 0b11 for high level. With bits 6:7 the amount of
bits that are shifted out per clock can be chosen. When a slice has multiple I/O pins this
value has to be set accordingly: 0b00 for 1 bit, 0b01 for 2 bits, 0b10 for 4 bits or 0b11 for
8 bits per clock.
4.2 Slice operation control registers
4.2.1 REGx
This is the data register. As long as a slice is enabled it will shift a data bit in or out at
every shift clock. Data is right shifted, data is shifted in at bit 31 and data is shifted out
from bit 0.
4.2.2 REG_SSx
This is the shadow register for the data. Every time a slice is done with sending or
receiving data it exchanges the data and shadow register. This way the shadow register
can be read or written at any time.
4.2.3 PRESETx
With the PRESETx register the SGPIO_CLOCK can be divided down to a lower speed.
To calculate the value for this register the following formula is used:
PRESETx value = (SGPIO_CLOCK speed / shift clock speed) – 1. When a 1.5 MHz
clock speed is required for a slice and a 12 MHz SGPIO clock is used the correct
PRESETx value is (12/1.5) – 1 = 7.
4.2.4 POSx
Each position register contains the position counter for one slice: POS0 to POS15
contain the counter for slice A (register 0) to slice P (register 15).
This register controls when the shadow register REG_SS content is exchanged with
main register REG.
It has [15:8] as the POS_PRESET value and [7:0] as the current data bit POS counter. At
each data bit shift, POS decrements by 1. When POS reaches zero, POS is restored with
its POS_PRESET value. This should be 31 when the main register and the shadow
register exchange after all 32 bits of data have shifted in or out.
But when concatenating k slices this value should be (0x20 * k -1). For example, when
concatenating 4 slices and every slice needs to shift in or out all of its 32-bit data, POSx
should be (32 * 4 - 1) = 127. Please refer to Fig 3 for some more details for this register.
Tip 4. Before a slice is started (using CTRL_ENABLE), POS should be set to the
POS_PRESET value.
4.2.5 MASK_A, MASK_H, MASK_I, MASK_P
The mask registers are used for the “on pattern match” interrupts. With some slices it is
possible to mask the data for the pattern match interrupts. Slices A, H, I and P support
this function.
Every bit that is 1 in this register will be masked. If this register contains the value
0b00001111 the first 4 bits will be masked for the pattern interrupt.
See chapter 6, SGPIO Interrupts for more information.
AN11275
Application note
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 7 November 2012
© NXP B.V. 2012. All rights reserved.
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