SSTUB32868 Datasheet, PDF (10/30 Pages) NXP Semiconductors – 1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications

NXP Semiconductors
SSTUB32868
1.8 V DDR2-800 configurable registered buffer with parity
[1] Data inputs = D1 to D5, D7, D9 to D12, D17 to D28 when C = 0.
Data inputs = D1 to D12, D17 to D20, D22, D24 to D28 when C = 1.
[2] Data outputs = Q1x to Q5x, Q7x, Q9x to Q12x, Q17x to Q28x when C = 0.
Data outputs = Q1x to Q12x, Q17x to Q20x, Q22x, Q24x to Q28x when C = 1.
7. Functional description
7.1 Function table
Table 4.
RESET
Function table (each flip-flop)
Inputs
DCS0^[2] DCS1^[2]
CSGEN
H
L
L
X
H
L
L
X
H
L
L
X
H
L
H
X
H
L
H
X
H
L
H
X
H
H
L
X
H
H
L
X
H
H
L
X
H
H
H
L
H
H
H
L
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
L
X or
X or X or floating
floating floating
CK
↑
↑
L or H
↑
↑
L or H
↑
↑
L or H
↑
↑
L or H
↑
↑
L or H
X or
floating
Outputs^[1]
CK Dn, DODTn, Qn QCS0x QCS1x QODTn,
DCKEn
QCKEn
↓
L
L
L
L
L
↓
H
H
L
L
H
L or H
X
Q₀
Q₀
Q₀
Q₀
↓
L
L
L
H
L
↓
H
H
L
H
H
L or H
X
Q₀
Q₀
Q₀
Q₀
↓
L
L
H
L
L
↓
H
H
H
L
H
L or H
X
Q₀
Q₀
Q₀
Q₀
↓
L
L
H
H
L
↓
H
H
H
H
H
L or H
X
Q₀
Q₀
Q₀
Q₀
↓
L
Q₀
H
H
L
↓
H
Q₀
H
H
H
L or H
X
Q₀
Q₀
Q₀
Q₀
X or X or floating L
L
L
L
floating
[1] Q₀ is the previous state of the associated output.
[2] DCS2 and DCS3 operate identically to DCS0 and DCS1, except they do not have corresponding re-driven (QCS) outputs.
SSTUB32868_4
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 04 — 22 April 2010
© NXP B.V. 2010. All rights reserved.
10 of 30