PCF8576C_10 Datasheet, PDF (10/57 Pages) NXP Semiconductors – Universal LCD driver for low multiplex rates

NXP Semiconductors
PCF8576C
Universal LCD driver for low multiplex rates
V_DD
R≤
t_r
2C_B
HOST
MICRO-
PROCESSOR/
MICRO-
CONTROLLER
SDA
SCL
OSC
VDD
VLCD
PCF8576C
40 segment drives _{LCD PANEL}
4 backplanes
(up to 160
elements)
A0 A1 A2 SA0 VSS
013aaa098
V_SS
Fig 7. Typical system configuration
The host microprocessor or microcontroller maintains the 2-line I²C-bus communication
channel with the PCF8576C.
Biasing voltages for the multiplexed LCD waveforms are generated internally, removing
the need for an external bias generator. The internal oscillator is selected by connecting
pin OSC to V_SS. The only other connections required to complete the system are the
power supplies (pins V_DD, V_SS, and V_LCD) and the LCD panel selected for the application.
7.1 Power-On-Reset (POR)
At power-on the PCF8576C resets to the following starting conditions:
• All backplane and segment outputs are set to V_DD
• The selected drive mode is 1:4 multiplex with ¹â„₃ bias
• Blinking is switched off
• Input and output bank selectors are reset (as defined in Table 8)
• The I²C-bus interface is initialized
• The data pointer and the subaddress counter are cleared
Remark: Do not transfer data on the I²C-bus for at least 1 ms after a power-on to allow
the reset action to complete.
7.2 LCD bias generator
The full-scale LCD voltage (V_oper) is obtained from V_DD − V_LCD. The LCD voltage may be
temperature compensated externally through the V_LCD supply to pin V_LCD.
Fractional LCD biasing voltages are obtained from an internal voltage divider comprising
three series resistors connected between V_DD and V_LCD. The center resistor can be
switched out of the circuit to provide a ¹â„₂ bias voltage level for the 1:2 multiplex
configuration.
PCF8576C
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 10 — 22 July 2010
© NXP B.V. 2010. All rights reserved.
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