LPC54102J256BD64QL Datasheet, PDF (10/90 Pages) NXP Semiconductors – 32-bit ARM Cortex-M4/M0+ MCU; 104 kB SRAM; 512 kB flash, 3 x I2C, 2 x SPI, 4 x USART, 32-bit counter/ timers, SCTimer/PWM, 12-bit 5.0 Msamples/sec ADC

NXP Semiconductors
Table 4. Pin description …continued
Symbol
Description
LPC5410x
32-bit ARM Cortex-M4/M0+ microcontroller
PIO0_5
PIO0_6
PIO0_7
PIO0_8
PIO0_9
PIO0_10
PIO0_11
C6 39 ^[2] PU I/O PIO0_5 — General-purpose digital input/output pin.
I U1_RXD — Receiver input for USART1.
O SCT0_OUT6 — SCT0 output 6. PWM output 6.
O CT32B0_MAT0 — 32-bit CT32B0 match output 0.
I R — Reserved.
D7 40 ^[2] PU I/O PIO0_6 — General-purpose digital input/output pin.
O U1_TXD — Transmitter output for USART1.
I R — Reserved.
O CT32B0_MAT1 — 32-bit CT32B0 match output 1.
I R — Reserved.
D6 41 ^[2] PU I/O PIO0_7 — General-purpose digital input/output pin.
I/O U1_SCLK — USART1 clock in synchronous USART mode.
O SCT0_OUT0 — SCT0 output 0. PWM output 0.
O CT32B0_MAT2 — 32-bit CT32B0 match output 2.
I R — Reserved.
I CT32B0_CAP2 — 32-bit CT32B0 capture input 2.
D5 43 ^[2] PU I/O PIO0_8 — General-purpose digital input/output pin.
I U2_RXD — Receiver input for USART2.
O SCT0_OUT1 — SCT0 output 1. PWM output 1.
O CT32B0_MAT3 — 32-bit CT32B0 match output 3.
I R — Reserved.
E7 44 ^[2] PU I/O PIO0_9 — General-purpose digital input/output pin.
O U2_TXD — Transmitter output for USART2.
O SCT0_OUT2 — SCT0 output 2. PWM output 2.
I CT32B3_CAP0 — 32-bit CT32B3 capture input 0.
I R — Reserved.
I/O SPI0_SSEL0 — Slave Select 0 for SPI0.
E6 45 ^[2] PU I/O PIO0_10 — General-purpose digital input/output pin.
I/O U2_SCLK — USART2 clock in synchronous USART mode.
O SCT0_OUT3 — SCT0 output 3. PWM output 3.
O CT32B3_MAT0 — 32-bit CT32B3 match output 0.
I R — Reserved.
E5 46 ^[2] PU I/O PIO0_11 — General-purpose digital input/output pin.
I/O SPI0_SCK — Serial clock for SPI0.
I U1_RXD — Receiver input for USART1.
O CT32B2_MAT1 — 32-bit CT32B2 match output 1.
I R — Reserved.
LPC5410x
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2.6 — 3 October 2016
© NXP B.V. 2016. All rights reserved.
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