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| 74AUP1T97 Datasheet, PDF (10/17 Pages) NXP Semiconductors – Low-power configurable gate with voltage-level translator | |||
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NXP Semiconductors
12. Waveforms
74AUP1T97
Low-power conï¬gurable gate with voltage-level translator
VI
A, B, C input
VM
VM
GND
VOH
t PHL
t PLH
Y output
VM
VM
VOL
VOH
t PLH
t PHL
Y output
VM
VM
VOL
001aab593
Measurement points are given in Table 10.
VOL and VOH are typical output voltage drop that occur with the output load.
Fig 12. Input A, B and C to output Y propagation delay times.
Table 10. Measurement points
Supply voltage
Output
VCC
2.3 V to 3.6 V
VM
0.5VCC
Input
VM
0.5VI
VI
1.65 V to 3.6 V
tr = tf
⤠3.0 ns
74AUP1T97_1
Product data sheet
Rev. 01 â 25 October 2007
© NXP B.V. 2007. All rights reserved.
10 of 17
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