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74AUP1T97 Datasheet, PDF (1/17 Pages) NXP Semiconductors – Low-power configurable gate with voltage-level translator | |||
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74AUP1T97
Low-power conï¬gurable gate with voltage-level translator
Rev. 01 â 25 October 2007
Product data sheet
1. General description
The 74AUP1T97 provides low-power, low-voltage conï¬gurable logic gate functions. The
output state is determined by eight patterns of 3-bit input. The user can choose the logic
functions MUX, AND, OR, NAND, NOR, inverter and buffer. All inputs can be connected to
VCC or GND.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 2.3 V to 3.6 V.
The 74AUP1T97 is designed for logic-level translation applications with input switching
levels that accept 1.8 V low-voltage CMOS signals, while operating from either a single
2.5 V or 3.3 V supply voltage.
The wide supply voltage range ensures normal operation as battery voltage drops from
3.6 V to 2.3 V.
This device is fully speciï¬ed for partial power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backï¬ow current through
the device when it is powered down.
Schmitt trigger inputs make the circuit tolerant to slower input rise and fall times across
the entire VCC range.
2. Features
s Wide supply voltage range from 2.3 V to 3.6 V
s High noise immunity
s ESD protection:
x HBM JESD22-A114E Class 3A exceeds 5000 V
x MM JESD22-A115-A exceeds 200 V
x CDM JESD22-C101C exceeds 1000 V
s Low static power consumption; ICC = 1.5 µA (maximum)
s Latch-up performance exceeds 100 mA per JESD 78 Class II
s Inputs accept voltages up to 3.6 V
s Low noise overshoot and undershoot < 10 % of VCC
s IOFF circuitry provides partial Power-down mode operation
s Multiple package options
s Speciï¬ed from â40 °C to +85 °C and â40 °C to +125 °C
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