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PHN210T Datasheet, PDF (1/7 Pages) NXP Semiconductors – Dual N-channel enhancement mode | |||
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Philips Semiconductors
Dual N-channel enhancement mode
TrenchMOSTM transistor
Product specification
PHN210T
FEATURES
⢠Dual device
⢠Low threshold voltage
⢠Fast switching
⢠Logic level compatible
⢠Surface mount package
SYMBOL
d1 d1 d2 d2
s1 g1 s2 g2
QUICK REFERENCE DATA
VDS = 30 V
ID = 3.4 A
RDS(ON) ⤠100 m⦠(VGS = 10 V)
RDS(ON) ⤠200 m⦠(VGS = 4.5 V)
GENERAL DESCRIPTION
Dual N-channel enhancement
mode field-effect transistor in a
plastic envelope using âtrenchâ
technology.
Applications:-
⢠Motor and relay drivers
⢠d.c. to d.c. converters
⢠Logic level translator
The PHN210T is supplied in the
SOT96-1 (SO8) surface mounting
package.
PINNING
PIN
DESCRIPTION
1 source 1
2 gate 1
3 source 2
4 gate 2
5,6 drain 2
7,8 drain 1
SOT96-1
876 5
pin 1 index
123 4
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
VDS
VDS
VDGR
VGS
ID
ID
IDM
Ptot
Tstg, Tj
Repetitive peak drain-source
voltage
Continuous drain-source voltage
Drain-gate voltage
Gate-source voltage
Drain current per MOSFET1
Drain current per MOSFET (both
MOSFETs conducting)1
Drain current per MOSFET (pulse
peak value)
Total power dissipation (either or
both MOSFETs conducting)1
Storage & operating temperature
Tj = 25 ËC to 150ËC
RGS = 20 kâ¦
Ta = 25 ËC
Ta = 70 ËC
Ta = 25 ËC
Ta = 70 ËC
Ta = 25 ËC
Ta = 25 ËC
Ta = 70 ËC
MIN.
-
-
-
-
-
-
-
-
-
-
-
- 65
MAX.
30
30
30
± 20
3.4
2.8
2.4
1.9
14
2
1.3
150
UNIT
V
V
V
V
A
A
A
A
A
W
W
ËC
1 Surface mounted on FR4 board, t ⤠10 sec
March 1999
1
Rev 1.000
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