PCA9665 Datasheet, PDF (1/90 Pages) NXP Semiconductors – Fm+ parallel bus to I2C-bus controller

PCA9665
Fm+ parallel bus to I²C-bus controller
Rev. 03 — 12 August 2008
Product data sheet
1. General description
The PCA9665 serves as an interface between most standard parallel-bus
microcontrollers/microprocessors and the serial I²C-bus and allows the parallel bus
system to communicate bidirectionally with the I²C-bus. The PCA9665 can operate as a
master or a slave and can be a transmitter or receiver. Communication with the I²C-bus is
carried out on a Byte or Buffered mode using interrupt or polled handshake. The
PCA9665 controls all the I²C-bus specific sequences, protocol, arbitration and timing with
no external timing element required.
The PCA9665 has the same footprint as the PCA9564 with additional features:
• 1 MHz transmission speeds
• Up to 25 mA drive capability on SCL/SDA
• 68-byte buffer
• I²C-bus General Call
• Software reset on the parallel bus
2. Features
I Parallel-bus to I²C-bus protocol converter and interface
I Both master and slave functions
I Multi-master capability
I Internal oscillator trimmed to 15 % accuracy reduces external components
I 1 Mbit/s and up to 25 mA SCL/SDA I_OL (Fast-mode Plus (Fm+)) capability
I I²C-bus General Call capability
I Software reset on parallel bus
I 68-byte data buffer
I Operating supply voltage: 2.3 V to 3.6 V
I 5 V tolerant I/Os
I Standard-mode and Fast-mode I²C-bus capable and compatible with SMBus
I ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115, and 1000 V CDM per JESD22-C101
I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
I Packages offered: DIP20, SO20, TSSOP20, HVQFN20