PCA9617A Datasheet, PDF (1/24 Pages) NXP Semiconductors – Level translating Fm+ I2C-bus repeater

PCA9617A
Level translating Fm+ I²C-bus repeater
Rev. 1 — 20 March 2013
Product data sheet
1. General description
The PCA9617A is a CMOS integrated circuit that provides level shifting between low
voltage (0.8 V to 5.5 V) and higher voltage (2.2 V to 5.5 V) Fast-mode Plus (Fm+) I²C-bus
or SMBus applications. While retaining all the operating modes and features of the
I²C-bus system during the level shifts, it also permits extension of the I²C-bus by providing
bidirectional buffering for both the data (SDA) and the clock (SCL) lines, thus enabling two
buses of 540 pF at 1 MHz or up to 4000 pF at lower speeds. Using the PCA9617A
enables the system designer to isolate two halves of a bus for both voltage and
capacitance. The SDA and SCL pins are overvoltage tolerant and are high-impedance
when the PCA9617A is unpowered.
The 2.2 V to 5.5 V bus port B drivers have the static level offset, while the adjustable
voltage bus port A drivers eliminate the static offset voltage. This results in a LOW on the
port B translating into a nearly 0 V LOW on the port A which accommodates the smaller
voltage swings of lower voltage logic.
The static offset design of the port B PCA9617A I/O drivers prevents them from being
connected to the static or incremented offset of other bus buffers. Port A of two or more
PCA9617As can be connected together, however, to allow a star topography with port A
on the common bus, and port A can be connected directly to any other buffer with static or
incremented offset outputs. Multiple PCA9617As can be connected in series, port A to
port B, with no build-up in offset voltage with only time of flight delays to consider.
The PCA9617A drivers are not enabled unless V_CC(A) is above 0.8 V and V_CC(B) is above
2.2 V. The EN pin is referenced to V_CC(B) and can also be used to turn the drivers on and
off under system control. Caution should be observed to only change the state of the
enable pin when the bus is idle.
The output pull-down on the port B internal buffer LOW is set for approximately 0.55 V,
while the input threshold of the internal buffer is set about 90 mV lower (0.45 V). When the
port B I/O is driven LOW internally, the LOW is not recognized as a LOW by the input.
This prevents a latching condition from occurring. The output pull-down on port A drives a
hard LOW and the input level is set at 0.35V_CC(A) to accommodate the need for a lower
LOW level in systems where the low voltage side supply voltage is as low as 0.8 V.
2. Features and benefits
 2 channel, bidirectional buffer isolates capacitance and allows 540 pF on either side of
the device at 1 MHz and up to 4000 pF at lower speeds
 Voltage level translation from 0.8 V to 5.5 V and from 2.2 V to 5.5 V
 Footprint and functional replacement for PCA9517A at Fast-mode speeds
 Port A operating supply voltage range of 0.8 V to 5.5 V with normal levels