GTL2002 Datasheet, PDF(1/22 Page) NXP Semiconductors – 2-bit bi-directional low voltage translator

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GTL2002 Datasheet, PDF (1/22 Pages) NXP Semiconductors – 2-bit bi-directional low voltage translator

GTL2002

2-bit bidirectional low voltage translator

Rev. 07 â 2 July 2009

Product data sheet

1. General description

The Gunning Transceiver Logic - Transceiver Voltage Clamps (GTL-TVC) provide

high-speed voltage translation with low ON-state resistance and minimal propagation

delay. The GTL2002 provides 2 NMOS pass transistors (Sn and Dn) with a common gate

(GREF) and a reference transistor (SREF and DREF). The device allows bidirectional

voltage translations between 1.0 V and 5.0 V without use of a direction pin.

When the Sn or Dn port is LOW the clamp is in the ON-state and a low resistance

connection exists between the Sn and Dn ports. Assuming the higher voltage is on the Dn

port, when the Dn port is HIGH, the voltage on the Sn port is limited to the voltage set by

the reference transistor (SREF). When the Sn port is HIGH, the Dn port is pulled to VCC by

the pull-up resistors. This functionality allows a seamless translation between higher and

lower voltages selected by the user, without the need for directional control.

All transistors have the same electrical characteristics and there is minimal deviation from

one output to another in voltage or propagation delay. This is a beneï¬t over discrete

transistor voltage translation solutions, since the fabrication of the transistors is

symmetrical. Because all transistors in the device are identical, SREF and DREF can be

located on any of the other two matched Sn/Dn transistors, allowing for easier board

layout. The translator's transistors provide excellent ESD protection to lower voltage

devices and at the same time protect less ESD-resistant devices.

2. Features

I 2-bit bidirectional low voltage translator

I Allows voltage level translation between 1.0 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5 V

buses, which allows direct interface with GTL, GTL+, LVTTL/TTL and 5 V CMOS levels

I Provides bidirectional voltage translation with no direction pin

I Low 6.5 â¦ ON-state resistance (Ron) between input and output pins (Sn/Dn)

I Supports hot insertion

I No power supply required; will not latch up

I 5 V tolerant inputs

I Low standby current

I Flow-through pinout for ease of printed-circuit board trace routing

I ESD protection exceeds 2000 V HBM per JESD22-A114, 150 V MM per

JESD22-A115, and 1000 V CDM per JESD22-C101

I Packages offered: SO8, TSSOP8 (MSOP8), VSSOP8, XQFN8U

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