74LVC2T45 Datasheet, PDF (1/32 Pages) NXP Semiconductors – Dual supply translating transceiver; 3-state

74LVC2T45; 74LVCH2T45
Dual supply translating transceiver; 3-state
Rev. 03 — 19 January 2010
Product data sheet
1. General description
The 74LVC2T45; 74LVCH2T45 are dual bit, dual supply translating transceivers with
3-state outputs that enable bidirectional level translation. They feature two data
input-output ports (nA and nB), a direction control input (DIR) and dual supply pins (V_CC(A)
and V_CC(B)). Both V_CC(A) and V_CC(B) can be supplied at any voltage between 1.2 V and
5.5 V making the device suitable for translating between any of the low voltage nodes
(1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V). Pins nA and DIR are referenced to V_CC(A) and
pins nB are referenced to V_CC(B). A HIGH on DIR allows transmission from nA to nB and a
LOW on DIR allows transmission from nB to nA.
The devices are fully specified for partial power-down applications using I_OFF. The I_OFF
circuitry disables the output, preventing any damaging backflow current through the
device when it is powered down. In suspend mode when either V_CC(A) or V_CC(B) are at
GND level, both A port and B port are in the high-impedance OFF-state.
Active bus hold circuitry in the 74LVCH2T45 holds unused or floating data inputs at a valid
logic level.
2. Features
„ Wide supply voltage range:
‹ V_CC(A): 1.2 V to 5.5 V
‹ V_CC(B): 1.2 V to 5.5 V
„ High noise immunity
„ Complies with JEDEC standards:
‹ JESD8-7 (1.2 V to 1.95 V)
‹ JESD8-5 (1.8 V to 2.7 V)
‹ JESD8C (2.7 V to 3.6 V)
‹ JESD36 (4.5 V to 5.5 V)
„ ESD protection:
‹ HBM JESD22-A114E Class 3A exceeds 4000 V
‹ MM JESD22-A115-A exceeds 200 V
‹ CDM JESD22-C101C exceeds 1000 V
„ Maximum data rates:
‹ 420 Mbps (3.3 V to 5.0 V translation)
‹ 210 Mbps (translate to 3.3 V))
‹ 140 Mbps (translate to 2.5 V)
‹ 75 Mbps (translate to 1.8 V)
‹ 60 Mbps (translate to 1.5 V)