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74AUP2G3404 Datasheet, PDF (1/19 Pages) NXP Semiconductors – Low-power buffer and inverter | |||
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74AUP2G3404
Low-power buffer and inverter
Rev. 1 â 22 August 2012
Product data sheet
1. General description
The 74AUP2G3404 is a single buffer and single inverter.
Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
2. Features and benefits
ï® Wide supply voltage range from 0.8 V to 3.6 V
ï® High noise immunity
ï® Complies with JEDEC standards:
ïµ JESD8-12 (0.8 V to 1.3 V)
ïµ JESD8-11 (0.9 V to 1.65 V)
ïµ JESD8-7 (1.2 V to 1.95 V)
ïµ JESD8-5 (1.8 V to 2.7 V)
ïµ JESD8-B (2.7 V to 3.6 V)
ï® ESD protection:
ïµ HBM JESD22-A114F Class 3A exceeds 5000 V
ïµ MM JESD22-A115-A exceeds 200 V
ïµ CDM JESD22-C101E exceeds 1000 V
ï® Low static power consumption; ICC = 0.9 ïA (maximum)
ï® Latch-up performance exceeds 100 mA per JESD 78 Class II
ï® Inputs accept voltages up to 3.6 V
ï® Low noise overshoot and undershoot < 10 % of VCC
ï® IOFF circuitry provides partial power-down mode operation
ï® Multiple package options
ï® Specified from ï40 ï°C to +85 ï°C and ï40 ï°C to +125 ï°C
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