M58LT128HST Datasheet, PDF (68/110 Pages) STMicroelectronics – 128-Mbit (8 Mb ×16, Multiple Bank, Multilevel interface, Burst) 1.8 V supply, Secure Flash memories

DC and AC parameters
M58LT128HST, M58LT128HSB
Table 25. Write AC characteristics, Chip Enable controlled⁽¹⁾
Symbol
Alt
Parameter
M58LT128HST/B
Unit
85
t_AVAV
t_WC Address Valid to Next Address Valid
Min
85
ns
t_AVEH
Address Valid to Chip Enable High
Min
50
ns
t_AVLH
Address Valid to Latch Enable High
Min
10
ns
t_DVEH
t_DS Data Valid to Chip Enable High
Min
50
ns
t_EHAX
t_AH Chip Enable High to Address Transition
Min
0
ns
t_EHDX
t_DH Chip Enable High to Input Transition
Min
0
ns
t_EHEL t_CPH Chip Enable High to Chip Enable Low
Min
25
ns
t_EHGL
Chip Enable High to Output Enable Low
Min
0
ns
t_EHWH t_CH Chip Enable High to Write Enable High
Min
0
ns
t_ELKV
Chip Enable Low to Clock Valid
Min
9
ns
t_ELEH
t_CP Chip Enable Low to Chip Enable High
Min
50
ns
t_ELLH
Chip Enable Low to Latch Enable High
Min
10
ns
t_ELQV
Chip Enable Low to Output Valid
Min
85
ns
t_GHEL
Output Enable High to Chip Enable Low
Min
17
ns
t_LHAX
Latch Enable High to Address Transition
Min
9
ns
t_LLLH
t_WHEL(2)
Latch Enable Pulse Width
Min
10
ns
Write Enable High to Chip Enable Low
Min
25
ns
t_WLEL
t_CS Write Enable Low to Chip Enable Low
Min
0
ns
t_EHVPL
Chip Enable High to V_PP Low
Min
200
ns
t_QVVPL
Output (Status Register) Valid to V_PP Low Min
0
ns
t_VPHEH t_VPS V_PP High to Chip Enable High
Min
200
ns
1. Sampled only, not 100% tested.
2. t_WHEL has this value when reading in the targeted bank or when reading following a Set Configuration
Register command. System designers should take this into account and may insert a software No-Op
instruction to delay the first read in the same bank after issuing any command and to delay the first read to
any address after issuing a Set Configuration Register command. If the first read after the command is a
Read Array operation in a different bank and no changes to the Configuration Register have been issued,
t_WHEL is 0 ns.
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