311760-10 Datasheet, PDF (38/54 Pages) Numonyx B.V – 128-Mbit W18 Family with Synchronous PSRAM

128-Mbit W18 Family with Synchronous PSRAM
9.3
PSRAM Control Registers
The PSRAM includes two control registers that define the PSRAM device operation. The
Bus Control Register (BCR) defines how the PSRAM interacts with the system memory
busy, and the Refresh Control Register (RCR) defines low-power refresh modes. Both
these registers are loaded with default values on power-up and can be updated at any
time using hardware or software access method.
9.3.1
PSRAM Bus Control Register
The Bus Control Register (BCR) specifies the interface configurations. The Bus Control
Register is programmed via the Set Control Register command (with CRE = 1 and
A[19:18] = 10b) and retains the stored information until it is reprogrammed or the
device loses power.
Reserved bit fields of the BCR should be ignored during a Fetch Control Register
command as they may have undefined values even when set to 0b with a Set Control
Register command. The BCR contents can only be set or changed when the PSRAM is in
idle state.
Table 14: PSRAM Bus Control Register Map
DQ
[15:0]
DQ1 DQ1 DQ1 DQ1 DQ1 DQ1 DQ DQ DQ DQ DQ DQ DQ DQ DQ DQ
5
4
3
2
1
0
9 87654 3210
A
A22
A17
[MAX:0 -
A1 A1 _-
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
]
A20 ^{9 8} A16
22-
17-
BCR Bit ₂₀ 19 18 ₁₆
15
14 13
12
11
10 9
8
7
654
32
10
Table 15: Bus Control Register Description
BCR Bit
NAME
22:20
19:18
17:16
Reserved
Register Select
Reserved
15
Operating Mode
14
Initial Latency
Description
Reserved bits should be set to ‘0’ during set control register commands
10 = Select BCR
Reserved bits should be set to ‘0’ during set control register commands
0 = Synchronous Burst Mode
1 = Asynchronous Mode (Default)
0 = Variable (Default)
1 = Fixed
Datasheet
38
November 2007
Order Number: 311760-10