M58PR512LE Datasheet, PDF (22/123 Pages) Numonyx B.V – 512-Mbit or 1-Gbit (× 16, multiple bank, multilevel, burst) 1.8 V supply Flash memories

Bus operations
M58PR512LE, M58PR001LE
Table 5. Bus operations⁽¹⁾
Operation
E G W L RP
DPD⁽²⁾
WAIT⁽³⁾
DQ15-DQ0
Bus read
Bus write
Address latch
V_IL V_IL V_IH V_IL(4) V_IH
V_IL V_IH V_IL V_IL(4) V_IH
V_IL X V_IH V_IL V_IH
De-
asserted⁽⁵⁾
De-
asserted⁽⁵⁾
De-
asserted⁽⁵⁾
Data output
Data input
Data output or Hi-Z⁽⁶⁾
Output disable
V_IL V_IH V_IH
X
V_IH
De-
asserted⁽⁵⁾
Hi-Z
Hi-Z
Standby
V_IH X X
X
V_IH
De-
asserted⁽⁵⁾
Hi-Z
Hi-Z
Reset
XXX
X
V_IL
De-
asserted⁽⁵⁾
Hi-Z
Hi-Z
Deep power-
down
V_IH X X
X
V_IH Asserted⁽⁷⁾
Hi-Z
Hi-Z
1. X = Don't care.
2. The DPD signal polarity depends on the value of the ECR14 bit.
3. WAIT signal polarity is configured using the Set Configuration Register command.
4. L can be tied to V_IH if the valid address has been previously latched.
5. If ECR15 is set to '0', the device cannot enter the deep power-down mode, even if DPD is asserted.
6. Depends on G.
7. ECR15 has to be set to ‘1’ for the device to enter deep power-down.
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