NTE3094 Datasheet, PDF (3/3 Pages) NTE Electronics – Optoisolator Dual, High Speed, Open Collector NAND Gate

Switching Characteristics: (T_A = +25°C, V_CC = 5V unless otherwise specified)
Parameter
Symbol
Test Conditions
Min Typ Max Unit
Propagation Delay Time
t_PLH I_F = 7.5mA, R_L = 350Ω,
t_PHL ^{CL = 15pF}
Note 8
Note 9
– 57 75 ns
– 45 75 ns
Output Rise Time (10% to 90%)
t_r I_F = 7.5mA, R_L = 350Ω, C_L = 15pF, Note 3
– 25 – ns
Output Fall Time (90% to 10%)
t_f
– 35 – ns
Common Mode Transient Immunity CM_H I_F = 0mA, V_O(min) = 2V
V_CM = 10V_P–P, – 500 – V/µs
CM_L I_F = 7.5mA, V_O(max) = 0.8V ^{RL = 350Ω}
– –500 – V/µs
Note 3. Each channel.
Note 8. The t_PLH propagation delay is measured from the 3.75mA point on the trailing edge of the
input pulse to the 1.5V point on the trailing edge of the output pulse.
Note 9. The t_PHL propagation delay is measured from the 3.75mA point on the leading edge of the
input pulse to the 1.5V point on the leading edge of the output pulse.
Note10. Common mode transient immunity in Logic High level is the maximum tolerable (positive)
dv cm/dt on the leading edge of the common mode pulse (V_CM) to assure that the output will
remain in a Logic High state (i.e. V_O 2.0V). Common mode transient immunity in Logic Low
level is the maximum tolerable (negative) dc cm/dt on the trailing edge of the common mode
pulse signal (V_CM) to assure that the output will remain in a Logic Low state (i.e. V_O 0.8V).
Pin Connection Diagram
Anode 1 1
8 ^V_CC
2
Cathode 1
Cathode 2 3
7 _{VO 1}
6 V_O 2
Anode 2 4
8
5 GND
5
.250 (6.35)
1
4
.020 (.508) Min
Seating
Plane
.390 (9.9) Max
.185
(4.7)
Max
.100 (2.54)
.115 (2.94) Min