NTE21128 Datasheet, PDF (3/6 Pages) NTE Electronics – Integrated Circuit NMOS, 128K (16K x 8) UV EPROM

AC Characteristics (Program, Program Verify, and Program Inhibit Modes):
(T_A = +25° ±5°C, V_CC = +5V ±5%, V_PP = +21V ±0.5V)
Parameter
Symbol
Test Conditions
Min Typ Max Unit
Address Setup Time
E Setup Time
Data Setup Time
Address Hold Time
t_AS Input Pulse Levels = 0.45V to 2.4V,
Input Timing Reference
t_{OES Level = 0.8V and 2V,}
t_DS
Output Timing Reference
Level = 0.8V and 2V,
t_AH ^{Input Rise and Fall Times: 20ns}
2 – – µs
2 – – µs
2 – – µs
0 – – µs
E Setup Time
t_CES
2 – – µs
Data Hold Time
t_DH
2 – – µs
Chip Enable to Output Float Delay t_DF
0 – 130 ns
Data Valid from E
t_OE
– – 150 ns
Program Pulse Width (Note 3)
t_PW
45 50 55 ms
V_PP Setup Time
t_VS
2 – – µs
Note 3. Initial Program Pulse width tolerance is 1msec ±5%.
Test Conditions:
Input Pulse Levels: 0.45V to 2.4V
Input Timing Reference Level: 0.8V and 2.0V
Output Timing Reference Level: 0.8V and 2.0V
Input Rise and Fall Times: 20ns
Capacitance: (T_A = +25°C, f = 1MHz)
Parameter
Symbol
Test Conditions
Input Capacitance
Output Capacitance
C_IN
C_OUT
V_IN = 0V
V_OUT = 0V
Min Typ Max Unit
– 4 8 pF
– 8 14 pF
Device Operation:
A single 5V power supply is required in the read mode. All inputs are TTL levels except for V_PP.
Read Mode
The NTE21128 has the following two control functions: Chip Enable (E) is the power control used for
device selection and Output Enable (G) is the output control used to gate data to the output pins, inde-
pendent of device selection.
Address access time (t_AVQV) is equal to the delay from E to output (t_ELQV). Data is available at the
outputs after the falling edge of G, assuming that E has been low and the addresses have been stable
for at least t_AVQV – t_GLQV.
Standby Mode
The standby mode, reducing the maximum active power current from 85mA to 40mA, is achieved by
applying a TTL high signal to the E input. When in the standby mode, the outputs are in a high imped-
ance state, independent of the G input.