LP38511-ADJ Datasheet, PDF (9/14 Pages) National Semiconductor (TI) – 800mA Fast-Transient Response Adjustable Low-Dropout Linear Voltage Regulator

causes the thermal shutdown circuit to respond to servo the
on/off cycling to a lower frequency. Please refer to the POW-
ER DISSIPATION/HEAT-SINKING section for power dissi-
pation calculations.
SETTING THE OUTPUT VOLTAGE
The output voltage is set using the external resistive divider
R1 and R2. The output voltage is given by the formula:
V_OUT = V_ADJ x (1 + (R1/R2))
(1)
The resistors used for R1 and R2 should be high quality, tight
tolerance, and with matching temperature coefficients. It is
important to remember that, although the value of V_ADJ is
guaranteed, the final value of V_OUT is not. The use of low
quality resistors for R1 and R2 can easily produce a V_OUT
value that is unacceptable.
It is recommended that the values selected for R1 and R2 are
such that the parallel value is less than 1.00 kΩ. This is to
reduce the possibility of any internal parasitic capacitances
on the ADJ pin from creating an undesirable phase shift that
may interfere with device stability.
( (R1 x R2) / (R1 + R2) ) ≤ 1.00 kΩ
(2)
FEED FORWARD CAPACITOR, C_FF
When using a ceramic capacitor for C_OUT, the typical ESR
value will be too small to provide any meaningful positive
phase compensation, F_Z, to offset the internal negative phase
shifts in the gain loop.
F_Z = 1 / (2 x π x C_OUT x ESR)
(3)
A capacitor placed across the gain resistor R1 will provide
additional phase margin to improve load transient response
of the device. This capacitor, C_FF, in parallel with R1, will form
a zero in the loop response given by the formula:
F_Z = 1 / (2 x π x C_FF x R1)
(4)
For optimum load transient response select C_FF so the zero
frequency, F_Z, falls between 20 kHz and 40 kHz.
C_FF = 1 / (2 x π x R1 x F_Z)
(5)
The phase lead provided by C_FF diminishes as the DC gain
approaches unity, or V_OUT approaches V_ADJ. This is because
C_FF also forms a pole with a frequency of:
F_P = 1 / (2 x π x C_FF x (R1 || R2) )
(6)
It's important to note that at higher output voltages, where R1
is much larger than R2, the pole and zero are far apart in fre-
quency. At lower output voltages the frequency of the pole
and the zero mover closer together. The phase lead provided
from C_FF diminishes quickly as the output voltage is reduced,
and has no effect when V_OUT = V_ADJ. For this reason, relying
on this compensation technique alone is adequate only for
higher output voltages.
Table 1 lists some suggested, best fit, standard ±1% resistor
values for R1 and R2, and a standard ±10% capacitor values
for C_FF, for a range of V_OUT values. Other values of R1, R2,
and C_FF are available that will give similar results.
TABLE 1.
V_OUT
0.80V
1.00V
1.20V
1.50V
1.80V
2.00V
2.50V
3.00V
3.30V
R1
1.07 kΩ
1.00 kΩ
1.40 kΩ
2.00 kΩ
2.94 kΩ
1.02 kΩ
1.02 kΩ
1.00 kΩ
2.00 kΩ
R2
1.78 kΩ
1.00 kΩ
1.00 kΩ
1.00 kΩ
1.13 kΩ
340Ω
255Ω
200Ω
357Ω
C_FF
4700 pF
4700 pF
3300 pF
2700 pF
1500 pF
4700 pF
4700 pF
4700 pF
2700 pF
F_Z
31.6 kHz
33.8 kHz
34.4 kHz
29.5 kHz
36.1 kHz
33.2 kHz
33.2 kHz
33.8 kHz
29.5 kHz
Please refer to Application Note AN-1378 Method For Calcu-
lating Output Voltage Tolerances in Adjustable Regulators for
additional information on how resistor tolerances affect the
calculated V_OUT value.
ENABLE OPERATION
The Enable ON threshold is typically 1.2V, and the OFF
threshold is typically 1.0V. To ensure reliable operation the
Enable pin voltage must rise above the maximum V_EN(ON)
threshold and must fall below the minimum V_EN(OFF) thresh-
old. The Enable threshold has typically 200 mV of hysteresis
to improve noise immunity.
The Enable pin (EN) has no internal pull-up or pull-down to
establish a default condition and, as a result, this pin must be
terminated either actively or passively.
If the Enable pin is driven from a single ended device (such
as the collector of a discrete transistor) a pull-up resistor to
V_IN, or a pull-down resistor to ground, will be required for
proper operation. A 1 kΩ to 100 kΩ resistor can be used as
the pull-up or pull-down resistor to establish default condition
for the EN pin. The resistor value selected should be appro-
priate to swamp out any leakage in the external single ended
device, as well as any stray capacitance.
If the Enable pin is driven from a source that actively pulls high
and low (such as a CMOS rail to rail comparator output), the
pull-up, or pull-down, resistor is not required.
If the application does not require the Enable function, the pin
should be connected directly to the adjacent V_IN pin.
POWER DISSIPATION/HEAT-SINKING
A heat-sink may be required depending on the maximum
power dissipation (P_D(MAX)), maximum ambient temperature
(T_A(MAX))of the application, and the thermal resistance (θ_JA) of
the package. Under all possible conditions, the junction tem-
perature (T_J) must be within the range specified in the Oper-
ating Ratings. The total power dissipation of the device is
given by:
P_D = ( (V_IN−V_OUT) x I_OUT) + ((V_IN) x I_GND)
(7)
where I_GND is the operating ground current of the device
(specified under Electrical Characteristics).
9
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