LP38511-ADJ Datasheet, PDF (10/14 Pages) National Semiconductor (TI) – 800mA Fast-Transient Response Adjustable Low-Dropout Linear Voltage Regulator

The maximum allowable junction temperature rise (ΔT_J) de-
pends on the maximum expected ambient temperature (T_A
(MAX)^{) of the application, and the maximum allowable junction}
temperature (T_J(MAX)):
ΔT_J = T_J(MAX) − T_A(MAX)
(8)
The maximum allowable value for junction to ambient Ther-
mal Resistance, θ_JA, can be calculated using the formula:
θ_JA = ΔT_J / P_D(MAX)
(9)
LP38511-ADJ is available in TO-263 THIN and PSOP-8 sur-
face mount packages. For a comparison of the TO-263 THIN
package to the standard TO-263 package see Application
Note AN-1797 TO-263 THIN Package. The thermal resis-
tance depends on amount of copper area, or heat sink, and
on air flow. See Application Note AN-1520 A Guide to Board
Layout for Best Thermal Resistance for Exposed Packages
for guidelines.
Heat-Sinking the TO-263 THIN (TJ) Package
The DAP of the TO-263 THIN package is soldered to the cop-
per plane for heat sinking. The TO-263 THIN package has a
θ_JA rating of 67°C/W, and a θ_JC rating of 2°C/W. The θ_JA rating
of 67°C/W includes the device DAP soldered to an area of
0.055 square inches (0.22 in x 0.25 in) of 1 ounce copper on
a two sided PCB, with no airflow. See JEDEC standard EIA/
JESD51-3 for more information.
Figure 1 shows a curve for the θ_JA of TO-263 THIN package
for different thermal via counts under the exposed DAP, using
a four layer PCB for heat sinking. The thermal vias connect
the copper area directly under the exposed DAP to the first
internal copper plane only. See JEDEC standards EIA/
JESD51-5 and EIA/JESD51-7 for more information.
30040836
FIGURE 2. θ_JA vs Copper Area for the TO-263 THIN
Package
Heat-Sinking The PSOP-8 Package
The DAP of the PSOP-8 package is soldered to the copper
plane for heat sinking. The LP38511MR package has a θ_JA
rating of 168°C/W, and a θ_JC rating of 11°C/W. The θ_JA rating
of 168°C/W includes the device DAP soldered to an area of
0.008 square inches (0.09 in x 0.09 in) of 1 ounce copper on
a two sided PCB, with no airflow. See JEDEC standard EIA/
JESD51-3 for more information.
Figure 3 shows a curve for different thermal via counts under
the exposed DAP, using a four layer PCB for heat sinking.
The thermal vias connect the copper area directly under the
exposed DAP to the first internal copper plane only. See
JEDEC standards EIA/JESD51-5 and EIA/JESD51-7 for
more information.
30040835
FIGURE 1. θ_JA vs Thermal Via Count for the TO-263 THIN
Package on 4–Layer PCB
Figure 2 shows the thermal performance when the TO-263
THIN is mounted to a two layer PCB where the copper area
is predominately directly under the exposed DAP. As shown
in the figure, increasing the copper area beyond 1 square inch
produces very little improvement.
30040837
FIGURE 3. θ_JA vs Thermal Via Count for the PSOP-8
Package on 4–Layer PCB
Figure 4 shows thermal performance for a two layer board
using thermal vias to a copper area on the bottom of the PCB.
The copper area on the top of the PCB, which is soldered to
the exposed DAP, is 0.10in x 0.20in, which is approximately
the same dimensions as the body of the PSOP-8 package.
The copper area on the bottom of the PCB is a square area
and is centered directly under the PSOP-8 package.
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