LM3710 Datasheet, PDF (9/16 Pages) National Semiconductor (TI) – Microprocessor Supervisory Circuits with Power Fail Input, Low Line Output, Manual Reset and Watchdog Timer

Typical Performance Characteristics (Continued)
Watchdog Timeout Period vs Temperature
(t_WD programmed as 6.2ms)
Low-Line Comparator Propagation Delay vs Temperature
Circuit Information
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Reset Output
The Reset input of a µP initializes the device into a known
state. The LM3710/LM3711 microprocessor supervisory cir-
cuits assert a forced reset output to prevent code execution
errors during power-up, power-down, and brownout condi-
tions.
RESET is guaranteed valid for V_CC > 1V. Once V_CC ex-
ceeds the reset threshold, an internal timer maintains the
output for the reset timeout period. After this interval, reset
goes high. The LM3710 offers an active-low RESET; The
LM3711 offers an active-high RESET.
Any time V_CC drops below the reset threshold (such as
during a brownout), the reset activates. When V_CC again
rises above the reset threshold, the internal timer starts.
Reset holds until V_CC exceeds the reset threshold for longer
than the reset timeout period. After this time, reset releases.
The Manual Reset input (MR) will initiate a forced reset also.
See the Manual Reset Input section.
Reset Threshold
The LM3710/LM3711 family is available with a reset voltage
of 3.08V. Other reset thresholds in the 2.20V to 5.0V range,
in steps of 10 mV, are available; contact National Semicon-
ductor for details.
Manual Reset Input (MR)
Many µP-based products require a manual reset capability,
allowing the operator to initiate a reset. The MR input is fully
debounced and provides an internal 56 kΩ pull-up. When the
MR input is pulled below V_MRT (1.225V) for more than 25 µs,
reset is asserted after a typical delay of 12 µs. Reset remains
active as long as MR is held low, and releases after the reset
timeout period expires after MR rises above V_MRT. Use MR
with digital logic to assert or to daisy chain supervisory
circuits. It may be used as another low-line comparator by
adding a buffer.
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Power-Fail Comparator (PFI/PFO)
The PFI is compared to a 1.225V internal reference, V_PFT. If
PFI is less than V_PFT, the Power Fail Output PFO drops low.
The power-fail comparator signals a falling power supply,
and is driven typically by an external voltage divider that
senses either the unregulated supply or another system
supply voltage. The voltage divider generally is chosen so
the voltage at PFI drops below V_PFT several milliseconds
before the main supply voltage drops below the reset thresh-
old, providing advanced warning of a brownout.
The voltage threshold is set by R₁ and R₂ and is calculated
as follows:
Note this comparator is completely separate from the rest of
the circuitry, and may be employed for other functions as
needed.
Low-Line Output (LLO)
The low-line output comparator is typically used to provide a
non-maskable interrupt to a µP when V_CC begins falling. LLO
monitors V_CC and goes low when V_CC falls below V_LLOT
(typically 1.02 • V_RST) with hysteresis of 0.0032 • V_RST.
Watchdog Timer Input (WDI)
The watchdog timer input monitors one of the microproces-
sor’s output lines for activity. Each time a transition occurs on
this monitored line, the watchdog counter is reset. However,
if no transition occurs and the timeout period is reached, the
LM3710/LM3711 assumes that the microprocessor has
locked up and the reset output is activated.
WDI is a high impedance input.
Special Precautions for the micro SMD Package
As with most integrated circuits, the LM3710 and LM3711
are sensitive to exposure from visible and infrared (IR) light
radiation. Unlike a plastic encapsulated IC, the micro SMD
package has very limited shielding from light, and some
sensitivity to light reflected from the surface of the PC board
or long wavelength IR entering the die from the side may be
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