LM3710 Datasheet, PDF (2/16 Pages) National Semiconductor (TI) – Microprocessor Supervisory Circuits with Power Fail Input, Low Line Output, Manual Reset and Watchdog Timer

Connection Diagram
MSOP-10
Top View
(looking from the coating side)
micro SMD 9 Bump Package
BPA09
20011802
20011801
Pin Descriptions
Pin No.
micro
SMD
MSOP
A1
2
Name
MR
B1
1
V_CC
C1
10
RESET
RESET
C2
8
PFO
C3
7
LLO
B3
5
A3
4
A2
3
B2
6, 9
GND
WDI
PFI
NC
Function
Manual-Reset input. When MR is less than V_MRT (Manual Reset Threshold)
RESET/RESET is engaged.
Power Supply input.
Reset Logic Output. Pulses low for t_RP (Reset Timeout Period) when triggered, and stays
low whenever V_CC is below the reset threshold or when MR is below V_MRT. It remains low
for t_RP after either V_CC rises above the reset threshold, or after MR input rises above
V_MRT (LM3710 only).
Reset Logic Output. RESET is the inverse of RESET (LM3711 only).
Power-Fail Logic Output. When PFI is below V_PFT, PFO goes low; otherwise, PFO
remains high.
Low-Line Logic Output. Early Power-Fail warning output. Low when V_CC falls below V_LLOT
(Low-Line Output Threshold). This output can be used to generate an NMI (Non-Maskable
Interrupt) to provide an early warning of imminent power-failure.
Ground reference for all signals.
Watchdog Input Transition Monitor: If no transition activity occurs for a period exceeding
t_WD (Watchdog Timeout Period), reset is engaged.
Power-Fail Comparator Input. When PFI is less than V_PFT (Power-Fail Reset Threshold),
the PFO goes low; otherwise, PFO remains high.
No Connect. Test input used at factory only. Leave floating.
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