DS90CR286A_09 Datasheet, PDF (9/14 Pages) National Semiconductor (TI) – +3.3V Rising Edge Data Strobe LVDS Receiver 28-Bit Channel Link-66 MHz, +3.3V Rising Edge Strobe LVDS Receiver 21-Bit Channel Link-66 MHz

C—Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max
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Tppos—Transmitter output pulse position (min and max)
RSKM = Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) (Note Cycle-to-cycle jitter is less than TBD ps at 66 MHz. ) + ISI (Inter-symbol interference)
(Note ISI is dependent on interconnect length; may be zero. )
Cable Skew—typically 10 ps–40 ps per foot, media dependent
Note 6: Cycle-to-cycle jitter is less than TBD ps at 66 MHz.
Note 7: ISI is dependent on interconnect length; may be zero.
FIGURE 11. Receiver LVDS Input Skew Margin
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