DS90CR286A_09 Datasheet, PDF (10/14 Pages) National Semiconductor (TI) – +3.3V Rising Edge Data Strobe LVDS Receiver 28-Bit Channel Link-66 MHz, +3.3V Rising Edge Strobe LVDS Receiver 21-Bit Channel Link-66 MHz

DS90CR286A Pin Descriptions —
MTD56 Package — 28-Bit Channel
Link Receiver
Pin Name
RxIN+
RxIN−
RxOUT
RxCLK IN+
RxCLK IN−
RxCLK OUT
PWR DOWN
V _CC
GND
PLL V _CC
PLL GND
LVDS V _CC
LVDS GND
I/O No
.
Description
I 4 Positive LVDS differentiaI data inputs.
I 4 Negative LVDS differential data inputs.
O 28 TTL level data outputs.
I 1 Positive LVDS differential clock input.
I 1 Negative LVDS differential clock input.
O 1 TTL Ievel clock output. The rising edge acts as data strobe.
I 1 TTL level input. When asserted (low input) the receiver outputs are low.
I 4 Power supply pins for TTL outputs.
I 5 Ground pins for TTL outputs.
I 1 Power supply for PLL.
I 2 Ground pin for PLL.
I 1 Power supply pin for LVDS inputs.
I 3 Ground pins for LVDS inputs.
DS90CR216A Pin Descriptions —
MTD48 Package — 21-Bit Channel
Link Receiver
Pin Name
RxIN+
RxIN−
RxOUT
RxCLK IN+
RxCLK IN−
RxCLK OUT
PWR DOWN
V _CC
GND
PLL V _CC
PLL GND
LVDS V _CC
LVDS GND
I/O No
.
Description
I 3 Positive LVDS differentiaI data inputs. (Note 8)
I 3 Negative LVDS differential data inputs. (Note 8)
O 21 TTL level data outputs.
I 1 Positive LVDS differential clock input.
I 1 Negative LVDS differential clock input.
O 1 TTL Ievel clock output. The rising edge acts as data strobe.
I 1 TTL level input. When asserted (low input) the receiver outputs are low.
I 4 Power supply pins for TTL outputs.
I 5 Ground pins for TTL outputs.
I 1 Power supply for PLL.
I 2 Ground pin for PLL.
I 1 Power supply pin for LVDS inputs.
I 3 Ground pins for LVDS inputs.
Note 8: These receivers have input failsafe bias circuitry to guarantee a stable receiver output for floating or terminated receiver inputs. Under these conditions
receiver inputs will be in a HIGH state. If a clock signal is present, outputs will all be HIGH; if the clock input is also floating/terminated outputs will remain in the
last valid state. A floating/terminated clock input will result in a LOW clock output.
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