DS90CR286A Datasheet, PDF (9/12 Pages) National Semiconductor (TI) – +3.3V Rising Edge Data Strobe LVDS Receiver 28-Bit Channel Link─66 MHz, +3.3V Rising Edge Strobe LVDS Receiver 21-Bit Channel Link─66 MHz

DS90CR286A Pin Description — 28-Bit Channel Link Receiver
Pin Name
RxIN+
RxIN−
RxOUT
RxCLK IN+
RxCLK IN−
RxCLK OUT
PWR DOWN
V _CC
GND
PLL V _CC
PLL GND
LVDS V _CC
LVDS GND
I/O
No.
I
4
I
4
O
28
I
1
I
1
O
1
I
1
I
4
I
5
I
1
I
2
I
1
I
3
Description
Positive LVDS differentiaI data inputs.
Negative LVDS differential data inputs.
TTL level data outputs.
Positive LVDS differential clock input.
Negative LVDS differential clock input.
TTL Ievel clock output. The rising edge acts as data strobe.
TTL level input. When asserted (low input) the receiver outputs are low.
Power supply pins for TTL outputs.
Ground pins for TTL outputs.
Power supply for PLL.
Ground pin for PLL.
Power supply pin for LVDS inputs.
Ground pins for LVDS inputs.
DS90CR216A Pin Description — 21-Bit Channel Link Receiver
Pin Name
RxIN+
RxIN−
RxOUT
RxCLK IN+
RxCLK IN−
RxCLK OUT
PWR DOWN
V _CC
GND
PLL V _CC
PLL GND
LVDS V _CC
LVDS GND
I/O
No.
I
3
I
3
O
21
I
1
I
1
O
1
I
1
I
4
I
5
I
1
I
2
I
1
I
3
Description
Positive LVDS differentiaI data inputs. (Note 8)
Negative LVDS differential data inputs. (Note 8)
TTL level data outputs.
Positive LVDS differential clock input.
Negative LVDS differential clock input.
TTL Ievel clock output. The rising edge acts as data strobe.
TTL level input. When asserted (low input) the receiver outputs are low.
Power supply pins for TTL outputs.
Ground pins for TTL outputs.
Power supply for PLL.
Ground pin for PLL.
Power supply pin for LVDS inputs.
Ground pins for LVDS inputs.
Note 8: These receivers have input failsafe bias circuitry to guarantee a stable receiver output for floating or terminated receiver inputs. Under these conditions re-
ceiver inputs will be in a HIGH state. If a clock signal is present, outputs will all be HIGH; if the clock input is also floating/terminated outputs will remain in the last
valid state. A floating/terminated clock input will result in a LOW clock output.
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