DS90CR286A Datasheet, PDF (3/12 Pages) National Semiconductor (TI) – +3.3V Rising Edge Data Strobe LVDS Receiver 28-Bit Channel Link─66 MHz, +3.3V Rising Edge Strobe LVDS Receiver 21-Bit Channel Link─66 MHz

Electrical Characteristics (Continued)
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for V_CC = 3.3V and T_A = +25C.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise speci-
fied (except V_OD and ∆V _OD).
Receiver Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Min
Typ
Max
Units
CLHT
CMOS/TTL Low-to-High Transition Time (Figure 2 )
2
5
ns
CHLT
CMOS/TTL High-to-Low Transition Time (Figure 2 )
1.8
5
ns
RSPos0 Receiver Input Strobe Position for Bit 0 (Figure 9,
f = 40 MHz
1.0
1.4
2.15
ns
Figure 10)
RSPos1 Receiver Input Strobe Position for Bit 1
4.5
5.0
5.8
ns
RSPos2 Receiver Input Strobe Position for Bit 2
8.1
8.5
9.15
ns
RSPos3 Receiver Input Strobe Position for Bit 3
11.6
11.9
12.6
ns
RSPos4 Receiver Input Strobe Position for Bit 4
15.1
15.6
16.3
ns
RSPos5 Receiver Input Strobe Position for Bit 5
18.8
19.2
19.9
ns
RSPos6 Receiver Input Strobe Position for Bit 6
22.5
22.9
23.6
ns
RSPos0 Receiver Input Strobe Position for Bit 0 (Figure 9,
f = 66 MHz
0.7
1.1
1.4
ns
Figure 10)
RSPos1 Receiver Input Strobe Position for Bit 1
2.9
3.3
3.6
ns
RSPos2 Receiver Input Strobe Position for Bit 2
5.1
5.5
5.8
ns
RSPos3 Receiver Input Strobe Position for Bit 3
7.3
7.7
8.0
ns
RSPos4 Receiver Input Strobe Position for Bit 4
9.5
9.9
10.2
ns
RSPos5 Receiver Input Strobe Position for Bit 5
11.7
12.1
12.4
ns
RSPos6 Receiver Input Strobe Position for Bit 6
13.9
14.3
14.6
ns
RSKM
RxIN Skew Margin (Note 4) (Figure 11 )
f = 40 MHz
490
ps
f = 66 MHz
400
ps
RCOP
RxCLK OUT Period (Figure 3)
15
T
50
ns
RCOH
RxCLK OUT High Time (Figure 3 )
f = 40 MHz
10.0
12.2
ns
RCOL
RxCLK OUT Low Time (Figure 3)
10.0
11.0
ns
RSRC
RxOUT Setup to RxCLK OUT (Figure 3 )
6.5
11.6
ns
RHRC
RxOUT Hold to RxCLK OUT (Figure 3 )
6.0
11.6
ns
RCOH
RxCLK OUT High Time (Figure 3 )
f = 66 MHz
5.0
7.6
ns
RCOL
RxCLK OUT Low Time (Figure 3)
5.0
6.3
ns
RSRC
RxOUT Setup to RxCLK OUT (Figure 3 )
4.5
7.3
ns
RHRC
RxOUT Hold to RxCLK OUT (Figure 3 )
4.0
6.3
ns
RCCD
RxCLK IN to RxCLK OUT Delay 25˚C, V_CC = 3.3V (Note 5)(Figure 4 )
3.5
5.0
7.5
ns
RPLLS Receiver Phase Lock Loop Set (Figure 5 )
10
ms
RPDD
Receiver Power Down Delay (Figure 8 )
1
µs
Note 4: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter pulse positions (min
and max) and the receiver input setup and hold time (internal data sampling window - RSPos). This margin allows for LVDS interconnect skew, inter-symbol inter-
ference (both dependent on type/length of cable), and clock jitter (less than 250 ps).
Note 5: Total latency for the channel link chipset is a function of clock period and gate delays through the transmitter (TCCD) and receiver (RCCD). The total latency
for the 215/285 transmitter and 216A/286A receiver is: (T + TCCD) + (2*T + RCCD), where T = Clock period.
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